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US 5,933,627 AGranted
Thread switch on blocked load or store using instruction thread field
AssigneeSun Microsystems, Inc.
InventorBodo Parady
Life of this patent
Estimating the term…
Abstract
A method and apparatus for switching between threads of a program in response to a long-latency event. In one embodiment, the long-latency events are load or store operations which trigger a thread switch if there is a miss in the level 2 cache. In addition to providing separate groups of registers for multiple threads, a group of program address registers pointing to different threads are provided. A switching mechanism switches between the program address registers in response to the long-latency events.
Claims10
A computer program product on a computer usable memory having computer readable code embodied thereon storing a plurality of instructions for access by a microprocessor for executing and changing instruction paths, comprising:
- a plurality of threads of instructions;
- at least one instruction type including a field identifying a thread;
- and
- at least a first instruction of said one instruction type, said one instruction being part of a first thread, and said field in said first instruction identifies a second thread to be switched to.
1 more element
A microprocessor comprising:
- a plurality of program address registers for storing an address corresponding to a thread;
- a plurality of groups of working registers, each group of working registers being assigned to a different thread;
- a plurality of load buffers, each load buffer being assigned to a different thread;
- and
- thread switching logic, configured to switch execution to an address in a one of said program address registers, and to switch between said groups of working registers, responsive to a switch signal which originates in response to designated instruction types, said designated instruction types having a program address register identified in an instruction field.
2 more elements
A microprocessor comprising:
- an instruction prefetch unit;
- an instruction cache, coupled to said instruction prefetch unit, for storing instructions for a plurality of threads;
- an instruction decode unit coupled to said instruction cache;
- a plurality of instruction buffers coupled to said instruction decode unit;
- an instruction dispatch unit coupled to said plurality of instruction buffers;
- a plurality of execution units, coupled to said instruction dispatch unit and arranged as a plurality of parallel pipelines;
- a level one data cache;
- a level two cache interface for providing addressing signals to a level two cache and receiving hit or miss signals from said level two cache;
- a plurality of program address registers for storing an address corresponding to a thread;
- a plurality of groups of working registers, each group of working registers being assigned to a different thread;
- a plurality of load buffers, each load buffer being assigned to a different thread;
- and
- thread switching logic, configured to switch execution to an address in a one of said program address registers, and to switch between said groups of working registers, responsive to a switch signal which originates in response to designated instruction types, said designated instruction types having a program address register identified in a thread switch instruction field;
- wherein said switch signal is a miss signal from said level two cache;
- wherein said designated instruction types include at least one of a load/store instruction and a jump instruction;
- wherein instructions in a thread other than said designated instruction types do not include an thread switch identification field identifying a program address register;
- wherein said program address register identified in an instruction field corresponds to a thread other than a thread of said instruction containing said instruction field.
14 more elements
A computer system comprising:
- a memory;
- a bus coupled to said memory;
- a microprocessor coupled to said bus, said microprocessor including
- a plurality of program address registers for storing an address corresponding to a thread;
- a plurality of groups of working registers, each group of working registers being assigned to a different thread;
- a plurality of load buffers, each load buffer being assigned to a different thread;
- and
- thread switching logic, configured to switch execution to an address in a one of said program address registers, and to switch between said groups of working registers, responsive to a switch signal which originates in response to designated instruction types, said designated instruction types having a program address register identified in an instruction field.
5 more elements
A method for operating a microprocessor, comprising the steps of:
- storing addresses corresponding to different threads in a plurality of program address registers;
- assigning each group of a plurality of groups of working registers to a different thread;
- and
- switching execution to an address in a one of said program address registers, and switching between said groups of working registers, responsive to a switch signal which originates in response to designated instruction types, said designated instruction types having a program address register identified in an instruction field.
1 more element
Dependencies are inferred from the claim text.