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AssigneeThe United States of America as represented by the Secretary of the Air Force
InventorKevin Anthony Kwiat
Estimating the term…
Computing modules can cooperate to tolerate faults among their members. In a preferred embodiment, computing modules couple with dual-ported memories and interface with a dynamically reconfigurable Field-Programmable Gate Array ("FPGA"). The FPGA serves as a computational engine to provide direct hardware support for flexible fault tolerance between unconstrained combinations of the computing modules. In addition to supporting traditional fault tolerance functions that require bit-for-bit exactness, the FPGA engine is programmed to tolerate faults that cannot be detected through direct comparison of module outputs. Combating these faults requires more complex algorithmic or heuristic approaches that check whether outputs meet user-defined reasonableness criteria. For example, forming a majority from outputs that are not identical but may nonetheless be correct requires taking an inexact vote. The FPGA engine's flexibility extends to allowing for multiprocessing among the modules where the FPGA engine supports message passing. Implementing these functions in hardware instead of software makes them execute faster. The FPGA is reprogrammable, and only the functions required immediately need be implemented. Inactive functions are stored externally in a Read-Only Memory (ROM). The dynamically reconfigurable FPGA gives the fault-tolerant system an output stage that offers low gate complexity by storing the unused "gates" as configuration code in ROM. Lower gate complexity translates to a highly reliable output stage, prerequisite to a fault tolerant system.
Apparatus for fault-tolerant multiprocessing, which comprises:
A method for multiprocessing in hardware that compensates for faults, comprising the steps of:
A method for multiprocessing that compensates for faults in hardware, comprising the steps of:
Apparatus for multiprocessing in hardware that compensates for faults, which comprises:
Apparatus for multiprocessing that compensates for faults in hardware, which comprises:
A method for reducing the duration of partial reconfiguration of a dynamically reconfigurable logic and switching device, which comprises the steps of:
Dependencies are inferred from the claim text.