US 5,930,523 A · Microcomputer having multiple bus structure coupling CPU to other processing elements

Abstract

A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.

Claims7

Dependent claims

A single-chip microcomputer comprising:

a central processing unit;
a cache memory;
a first bus coupled to the central processing unit and the cache memory;
a direct memory access control circuit;
an external bus interface for an external bus;
a second bus coupled to the direct memory access control circuit and the external bus interface;
a first controller coupled between the first bus and the second bus and including an address transceiver circuit which selectively transmits to the second bus an address signal provided from the central processing unit onto the first bus;
a peripheral module;
a third bus coupled to the peripheral module;
and
a second controller which is coupled between the second bus and the third bus and which effects a signal transfer between the second bus and the third bus.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application

09/055,099Filed 3 Apr 1998 · continuation

Priority

JP 5-25509917 Sep 1993

Granted

27 Jul 1999

Term ends

Not estimatedThe source records don’t support an estimate.

Classification12 codes

G06F 9/3001
To perform operations on data operands: arithmetic instructions
G06F 12/0893
Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches: caches…
G06F 13/36
Handling requests for interconnection or transfer: for access to common bus or bus system
G06F 13/405
Using bus bridges: where the bridge performs a synchronising function

Microcomputer having multiple bus structure coupling CPU to other processing elements

Life of this patent

Microcomputer having multiple bus structure coupling CPU to other processing elements

Life of this patent

Abstract

Claims7