Method and apparatus for performing binary translation

A method executed in a computer system for performing binary translation of a first binary image associated with a first computer architecture having a first instruction set to a second binary image associated with a second computer architecture having a second instruction set, the method comprising the steps of:

• translating, in accordance with profile execution information produced from a runtime execution of said first binary image by a runtime interpreter, a first portion of said first binary image to a second portion of said second binary image by producing a plurality of intermediate representations, each of said plurality of intermediate representations including one or more intermediate elements, each of said intermediate elements associated with a set of invariant characteristics remaining constant throughout said translating step, said set of invariant characteristics including at least two invariant characteristics, said at least two invariant characteristics including correspondence to an instruction included in said second instruction set, and correspondence to an instruction in said first instruction set, said translating step including the substeps of:
• producing an initial intermediate representation of said first portion;
• producing a final intermediate representation of said first portion, said initial and said final intermediate representations being of said plurality of intermediate representations;
• and
• optimizing said initial intermediate representation, substeps of optimizing and translating being intermixed to produce said final intermediate representation;
• and
• generating said second portion of said second binary image using said final intermediate representation, said profile execution information characterizing said runtime execution of said first binary image;
• wherein said initial and final intermediate representations include a list of instruction code cells, each of said instruction code cells including an instruction opcode and one or more code cell operands, said first computer architecture being a complex instruction set computer and said second computer architecture being a reduced instruction set computer, and wherein a machine instruction included in said first portion of said first binary image corresponds to one or more instruction code cells in said initial intermediate representation, and wherein said step of producing said initial intermediate representation includes the substeps of:
• associating an exception bit flag with each of said instruction code cells;
• initializing, as indicated in an opcode exception table, each of said exception bit flags, each of said exception bit flags being set to a bit value of 1 when said opcode exception table indicates a runtime exception can be generated when a machine instruction, which is in said first instruction set and corresponds to the instruction opcode, is executed, otherwise each of said exception bit flags being set to a bit value of 0, said opcode exception table being indexed by instruction opcode and having an entry for each instruction opcode corresponding to an instruction in said first instruction set;
• examining each machine instruction included in said first portion of said first binary image to determine memory operands, each of said memory operands representing a memory location;
• determining for each of said memory operands an effective address formation to reference a corresponding memory location;
• selecting for each of said memory operands one of a load operation or a store operation, the load operation being used to read from the corresponding memory location, and the store operation being used to write to the corresponding memory location;
• determining for each machine instruction a functional operation performed by said each machine instruction;
• generating, for each of said memory operands, a first instruction code cell and a second instruction code cell, said first instruction code cell computing the corresponding to the effective address formation, said second instruction code cell performing said selected one of said load operation or said store operation;
• generating, for said each machine instruction, a third instruction code cell corresponding to said functional operation performed by said machine instruction;
• and
• recording with each of said instruction code cells a first binary image address corresponding to the machine instruction from which said each instruction code cell is generated.