Method and apparatus for performing operative testing on an integrated circuit

A test system, comprising:

• a first die integrated on a first portion of a wafer;
• a monitor circuit integrated on a second portion of the wafer wherein the second portion of the wafer is separate from the first portion of the wafer, the monitor circuit performing a test operation which verifies a specified functional operation of the first die, wherein the test operation measures a current drawn by the first die;
• and
• a test device which is coupled to the first die and to the monitor circuit to selectively enable the monitor circuit to perform the test operation which verifies the specified functional operation of the first die.

A method for executing a test operation, comprising the steps of:

• integrating a first die on a first portion of a wafer;
• integrating a monitor circuit on a second portion of the wafer wherein the second portion of the wafer is separate from the first portion of the wafer;
• and
• enabling the monitor circuit to perform a test operation which measures a current drawn from the first die to verify an intended operation of the first die.

A data processor, comprising:

• control means for providing a mode control signal to indicate when the data processor operates in a first mode and a second mode of operation;
• an output buffer coupled to the control means for receiving the mode control signal and the output buffer receiving a known operating voltage, a portion of the output buffer providing a signal externally when the mode control signal indicates the data processor operates in the first mode of operation and the portion of the output buffer removing the known operating voltage provided to the data processor when the mode control signal indicates the data processor operates in the second mode of operation;
• and
• monitoring means for monitoring a decay of the known operating voltage to determine whether the data processor discharges an excessive amount of current.

A method for testing a data processor, comprising the steps of:

• receiving a known operating voltage at an output buffer;
• providing a mode control signal to indicate when the data processor operates in a first mode and a second mode of operation using a mode control circuit;
• enabling a portion of the output buffer to provide a signal externally when the mode control signal indicates the data processor operates in the first mode of operation;
• enabling the portion of the output buffer to remove the known operating voltage provided to the data processor when the mode control signal indicates the data processor is operating in the second mode of operation;
• and
• monitoring a decay of the known operating voltage to determine whether the data processor discharges an excessive amount of current.

A wafer, comprising:

• a pattern generator for providing an input stimulus, the pattern generator being integrated on a first portion of the wafer;
• a circuit to be tested coupled to the pattern generator to receive the input stimulus, the circuit to be tested providing an output which is a specified function of the input stimulus, the circuit to be tested being integrated on a second portion of the wafer wherein the second portion of the wafer is separate from the first portion of the wafer;
• and
• a signature analyzer coupled to the circuit to be tested to receive the output, the signature analyzer verifies the output is correct, the signature analyzer being integrated on the second portion of the wafer.

A die comprising:

• an integrated circuit;
• a current monitor circuit having a voltage controlled current switch, the current monitor circuit performing a first test operation which verifies an intended operation of the integrated circuit, wherein the first test operation measures a current drawn by the first die to determine a first current measurement and uses the first current measurement to verify a functional integrity of the first die;
• and
• a stimulus generator, the stimulus generator applying a set of test signals internal to the integrated circuit.