Method for manufacturing a semiconductor device with stabilization of a bipolar transistor and a schottky barrier diode

A method for manufacturing a BiCMOS device, comprising:

• forming a first, second and third semiconductor layers partitioned on a semiconductor substrate, said first semiconductor layer defining a region where a PMOS transistor is formed, said second semiconductor layer defining a region where an NMOS transistor is formed, said third semiconductor layer defining a region where a bipolar transistor is formed;
• forming a gate insulating layer on said first and second semiconductor layers;
• forming a first and second gate electrodes on said gate insulating layer for said PMOS transistor and said NMOS transistor respectively;
• forming an insulating layer on said first and second gate electrodes;
• etching back said insulating layer by reactive ion etching leaving said insulating layer as sidewall spacers only on sidewalls of said first and second gate electrodes;
• and
• etching parts of said first, second and third semiconductor layers by wet etching using said first and second gate electrodes and said sidewall spacers as a mask.

A method for manufacturing a MOS device and a Schottky barrier diode, comprising:

• forming a first and second semiconductor layers partitioned on a semiconductor substrate, said first semiconductor layer defining a region where a MOS transistor is formed, said second semiconductor layer defining a region where an SBD is formed;
• forming a gate insulating layer on said first and second semiconductor layers;
• forming a gate electrode on said gate insulating layer for said MOS transistor;
• forming an insulating layer on said gate electrode;
• etching back said insulating layer by reactive ion etching leaving said insulating layer as a sidewall spacer only on a sidewall of said gate electrode;
• and
• etching said first and second semiconductor layers by wet etching using said gate electrode and said sidewall spacer as a mask.

A method for manufacturing a CMOS device and a Schottky barrier diode, comprising:

• forming a first, second and third semiconductor layers partitioned on a semiconductor substrate, said first semiconductor layer defining a region where a PMOS transistor is formed, said second semiconductor layer defining a region where an NMOS transistor is formed, said third semiconductor layer defining a region where an SBD is formed;
• forming a gate insulating layer on said first and second semiconductor layers;
• forming a first and second gate electrodes on said gate insulating layer for said PMOS transistor and said NMOS transistor, respectively;
• forming an insulating layer on said first and second gate electrodes;
• etching back said insulating layer by reactive ion etching leaving said insulating layer as sidewall spacers only on sidewalls of said first and second gate electrodes;
• and
• etching said first, second and third semiconductor layers by wet etching using said first and second gate electrodes and said sidewall spacers as a mask.