Apparatus for clock shifting in an integrated transceiver

A radio, comprising:

• a microcontroller unit (MCU) receiving a MCU clock signal, the MCU generating internal subdivided MCU clock signals;
• memory coupled to the MCU for storing channel information, said channel information including predetermined MCU clock shifter ratios and predetermined switched capacitor clock shifter ratios;
• a frequency selector for selecting a frequency channel, the frequency selector being coupled to the MCU, the channel information being downloaded from memory into the MCU for the selected frequency channel;
• the MCU programming data representing the MCU clock shifter ratios and the switched capacitor clock shifter ratios for the selected frequency channel;
• a reference oscillator providing a reference frequency;
• a transceiver coupled to the MCU, the transceiver including:
• a serial register for receiving the data representing the MCU clock shifter ratios and the switched capacitor clock shifter ratios;
• a first clock shifter circuit coupled to the serial register and the reference oscillator, the first clock shifter circuit being programmed through the serial register to generate the MCU clock signal;
• a second clock shifter circuit coupled to the serial register and the reference oscillator, the second clock shifter circuit being programmed through the serial register to provide a switched capacitor clock frequency;
• a plurality of switched capacitor circuits responsive to the switched capacitor clock frequency;
• the MCU reprogramming, through the serial register, the first clock shifter circuit to generate a shifted MCU clock frequency in response to the selected frequency channel being susceptible to predetermined spurious harmonics of the MCU clock signal or internal subdivisions of the MCU clock signal;
• and
• the MCU reprogramming, through the serial register, the second clock shifter circuit to generate a shifted switched capacitor clock frequency in response to the selected frequency channel being susceptible to predetermined spurious harmonics of the switched capacitor clock frequency or subdivisions of the switched capacitor clock frequency.

A radio, comprising:

• a microcontroller unit (MCU) for receiving a MCU clock signal;
• a memory coupled to the MCU;
• a serial register coupled to the MCU;
• a first clock shifter circuit coupled to the serial register and generating the MCU clock signal;
• a second clock shifter circuit coupled to the serial register to provide a switched capacitor clock frequency;
• a plurality of switched capacitor circuits responsive to the switched capacitor clock frequency;
• a frequency selector for selecting a frequency channel, the MCU reprogramming, through the serial register, the first clock shifter circuit to generate a shifted MCU clock frequency in response to the selected frequency channel being susceptible to internal subdivisions of the MCU clock signal;
• and
• the MCU reprogramming, through the serial register, the second clock shifter circuit to generate a shifted switched capacitor clock frequency in response to the selected frequency channel being susceptible to predetermined spurious harmonics of the switched capacitor clock frequency or subdivision of the switched capacitor clock frequency.