Processor for executing instruction sets received from a network or from a local memory

A dual instruction set processor configured to communicatively connect to a network and to a local memory, and operable in one of two modes, said dual instruction set processor comprising:

• a first computer platform independent instruction decoder configured to decode instructions in a first computer platform independent instruction set, and to generate first decoded instructions in response thereto;
• a second instruction decoder configured to decode instructions in a second instruction set and to generate second decoded instructions in response thereto;
• an instruction execution unit configured to execute said first decoded instructions and said second decoded instructions;
• wherein in a first mode of operation, said first computer platform independent instruction decoder and said instruction execution unit operate upon computer platform independent instructions received from said network;
• and
• in a second mode of operation said first instruction decoder, said second instruction decoder, and said instruction execution unit operate upon instructions received from said local memory.

A computer system capable of being communicatively connected to a public carrier network, said computer system comprising:

• a communication interface unit capable of being communicatively connected to said public carrier network and capable of receiving a first set of computer platform independent instructions;
• a memory capable of storing a computer program of a second set of instructions, said second set of instructions being collectively different from said first set of instructions;
• a microprocessor connected to said communication interface unit to receive said first set of computer platform independent instructions therefrom;
• and connected to said memory to receive said second set of instructions therefrom;
• said microprocessor comprising:
• a first computer platform independent instruction decoder configured to decode computer platform independent instructions in said first set and to generate first decoded instructions in response thereto;
• a second instruction decoder configured to decode instructions in said second set and to generate second decoded instructions in response thereto;
• and
• an instruction execution unit configured to execute said first decoded instructions and said second decoded instructions.

A dual instruction set processor comprising:

• a first computer platform independent instruction decoder capable of decoding a first plurality of computer platform independent instructions;
• a stack, cooperating with said first computer platform independent instruction decoder;
• a second instruction decoder capable of decoding a second plurality of instructions;
• a flat register, cooperating with said second instruction decoder;
• and
• an instruction execution unit cooperating with said stack and said flat register to execute said first plurality of computer platform independent instructions and said second plurality of instructions.