Fault tolerant circuit arrangements

Abstract

A fault tolerant circuit arrangement comprises a plurality of replicated non-redundant shift registers 30 connected in parallel and each having an enable/configuration input 31 and a plurality of outputs 36. Furthermore each register 30 includes a verify output 32 for outputting a verify signal indicating whether or not a fault condition is present within the register. The arrangement also includes a verification signal generator 33 for applying a fixed reference signal, a comparator 34 to which the verify signals from the outputs 32 are applied, and a control circuit 35. The test/control-logic of the comparator 34 and control circuit 35 is constructed using masking redundancy 20-24 in order to render the test/control logic tolerant to faults. The control circuit 35 serves to control testing of each of the registers 30 in turn by supplying an enable signal to the input 31 of each register 30 beginning with the first register. This causes the supply of a verify signal V.sub.1 from the verify output 32 of the first register 30 to the comparator 34 which compares the verify signal V.sub.1 to the reference signal. If the verify signal V.sub.1 is significantly different from the reference signal, this indicates that there is a fault present in the first register, and the control circuit 35 is caused to supply a disable signal to the input 31 of the first register. The test procedure is repeated for each register 30 until a verify signal is received by the comparator 34 which indicates that there is no fault present in the associated register.

Dependencies are inferred from the claim text.