Chalcogenide memory cell with a plurality of chalcogenide electrodes
AssigneeMicron Technology, Inc.
InventorAlan R. Reinberg
Life of this patent
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Abstract
A chalcogenide memory cell with chalcogenide electrodes positioned on both sides of the active chalcogenide region of the memory cell. The chalcogenide memory cell includes upper and lower chalcogenide electrodes with a dielectric layer positioned therebetween. The dielectric layer includes an opening defining a pore. A volume of chalcogenide material formed integral to the upper chalcogenide electrode is contained within the pore. The upper and lower chalcogenide electrodes both have greater cross sectional areas than the pore.
Claims25
A method of fabricating a chalcogenide memory cell, comprising the acts of:
- providing a first layer of a given chalcogenide material;
- applying a layer of dielectric material onto the first layer of the given chalcogenide material;
- removing a portion of the layer of dielectric material to define an aperture;
- and
- applying a second layer of the given chalcogenide material onto the dielectric material and into the aperture.
A method of fabricating a memory cell, comprising the acts of:
- providing a diode assembly including a plurality of vertically aligned material layers;
- and
- providing a resistive assembly arranged in vertical alignment with the diode assembly, the resistive assembly in electrical communication with the diode assembly, the act of providing a resistive assembly comprising the acts of:
- providing a first layer of a given chalcogenide material;
- applying a layer of a dielectric material onto the first layer of the given chalcogenide material;
- and
- applying a second layer of the given chalcogenide material onto the layer of the dielectric material;
- wherein the layer of dielectric material is configured to restrict an area of electrical communication between the first and second layers of the given chalcogenide material.
A method of fabricating a memory cell comprising the acts of:
- (a) forming an access device;
- (b) forming a first electrode being electrically coupled to the access device;
- (c) forming a first layer of a given phase-changing material being electrically coupled to the first electrode;
- (d) forming a dielectric layer over the first layer of the given phase-changing material, the dielectric layer having an aperture therein;
- (e) forming a second layer of the given phase-changing material within the aperture and being electrically coupled to the first layer of the given phase-changing material;
- and
- (f) forming a second electrode being electrically coupled to the second layer of the given phase-changing material.
A method of fabricating a memory element of a memory cell comprising the acts of:
- (a) forming a first layer of a given phase-changing material;
- (b) forming a dielectric layer over the first layer of the given phase-changing material, the dielectric layer having an aperture therein;
- and
- (c) forming a second layer of the given phase-changing material within the aperture and being electrically coupled to the first layer of the given phase-changing material.
A method of fabricating a memory cell comprising the acts of:
- (a) forming an access device;
- (b) forming a first electrode being electrically coupled to the access device;
- (c) forming a first layer of a given resistive memory material being electrically coupled to the first electrode;
- (d) forming a dielectric layer over the first layer of the given resistive memory material, the dielectric layer having an aperture therein;
- (e) forming a second layer of the given resistive memory material within the aperture and being electrically coupled to the first layer of the given resistive memory material;
- and
- (f) forming a second electrode being electrically coupled to the second layer of the given resistive memory material.
A method of fabricating a memory element of a memory cell comprising the acts of:
- (a) forming a first layer of a given resistive memory material;
- (b) forming a dielectric layer over the first layer of the given resistive memory material, the dielectric layer having an aperture therein;
- and
- (c) forming a second layer of the given resistive memory material within the aperture and being electrically coupled to the first layer of the given resistive memory material.
Dependencies are inferred from the claim text.