Register-based redundancy circuit and method for built-in self-repair in a semiconductor memory device

A semiconductor memory having an array of memory elements including redundant memory elements, said semiconductor memory comprising:

• built-in self-test (BIST) circuitry operable to test, after packaging of said semiconductor memory, said memory elements and to generate first address signals indicative of a failed group of said memory elements, said failed group including at least one failed memory element;
• a failed address register coupled to a redundant group of said redundant memory elements, said failed address register coupled into an addressing path of said semiconductor memory and coupled to said BIST circuitry to receive and store said first address signals;
• redundant group selection circuitry including a TRUE comparator coupled to select said redundant group when a second address on said addressing path corresponds to said stored first address;
• and
• a NOT comparator coupled to enable a normal row predecoder when said second address does not correspond to said stored first address.

A self-repairing integrated circuit chip comprising:

• an array of semiconductor memory elements including normal and redundant memory elements;
• built-in self-test (BIST) circuitry operable to test, after packaging of said integrated circuit chip, memory elements defined therein and to generate first address signals indicative of a failed group of said memory elements;
• a redundancy register coupled to a redundant group of said redundant memory elements, said redundancy register coupled into an addressing path of said memory elements and coupled to said BIST circuitry to receive and store said first address signals;
• a TRUE comparator circuit coupled to select, without address substitution, said redundant group when a second address supplied to said array on said addressing path corresponds to said stored first address;
• and
• a NOT comparator circuit coupled to enable address decode circuits when said second address does not correspond to said stored first address.

An apparatus comprising:

• a semiconductor memory array;
• failed row address encoding means;
• built-in self-test (BIST) means operable to test, after packaging of said semiconductor memory array, memory elements defined therein and to enter into said failed row address encoding means an address of a row, if any, failing said test;
• row predecoder means coupled a row address path to at least partially decode a row address for application to said semiconductor memory array, said row predecoder means including a first enable terminal;
• redundant row selection means;
• NOT comparator means coupled to said row address path of said semiconductor memory and coupled to supply said first enable terminal with an enable signal when a row address mismatches a failed row address in said failed row address encoding means;
• and
• TRUE comparator means distinct from said NOT comparator means and coupled to said row address path to supply, via said redundant row selection means, a decode signal selective for a redundant row when said row address matches said failed row address.