Multi-standard decompression and/or compression device

A decoder for decompressing a compressed frame, the decoder coupled to a memory and to a processor comprising:

• a parser, for parsing the compressed frame and separating motion compensation information and block data structures in the compressed frame having a first and second output;
• a block decoder for decoding pixels and interpicture prediction errors in the block data structures, having an input coupled to the first output of the parser having an IDCT module having an input coupled to the block array and an output coupled to the output of the block decoder;
• a motion compensation engine for obtaining a prediction macroblock using the motion compensation information, having an input coupled to the second output of the parser;
• and
• a summing circuit for summing the decoded interpicture prediction errors and the prediction macroblock, having a first input coupled to an output of the decoder module and a second input coupled to an output of the motion compensation engine, and
• an encoder coupled to the memory, the encoder including the IDCT module.

A decoder for decompressing a compressed frame, the decoder coupled to a memory and to a processor comprising:

• a parser, for parsing the compressed frame and separating motion compensation information and block data structures in the compressed frame having a first and second output;
• a block decoder for decoding pixels and interpicture prediction errors in the block data structures, having an input coupled to the first output of the parser having an IDCT module having an input coupled to the block array and an output coupled to the output of the block decoder;
• a motion compensation engine for obtaining a prediction macroblock using the motion compensation information, having an input coupled to the second output of the parser;
• a summing circuit for summing the decoded interpicture prediction errors and the prediction macroblock, having a first input coupled to an output of the decoder module and a second input coupled to an output of the motion compensation engine;
• an encoder coupled to the memory, the encoder including the IDCT module;
• and
• an encoder including the motion compensation engine.

A computer comprising:

• an input device;
• an output device;
• a processor;
• a memory;
• and,
• a decoder having:
• a parser, for parsing the compressed frame and separating motion compensation information and block data structures in the compressed frame having a first and second output;
• a block decoder for decoding pixels and interpicture prediction errors in the block data structures, having an input coupled to the first output of the parser having an IDCT module having an input coupled to the block array and an output coupled to the output of the block decoder;
• a motion compensation engine for obtaining a prediction macroblock using the motion compensation information, having an input coupled to the second output of the parser;
• and
• a summing circuit for summing the decoded interpicture prediction errors and the prediction macroblock, having a first input coupled to an output of the decoder module and a second input coupled to an output of the motion compensation engine.

A method for operating a decoder having access to a memory and to a processor, and having a block decoder, a motion compensation engine, a summing circuit having a first input coupled to an output of the block decoder and a second input coupled to an output of the motion compensation engine comprising the steps of:

• decompressing the compressed frame in the block decoder;
• and
• responsive to the compressed frame comprising a frame including motion compensation prediction errors:
• decompressing any frames needed to decompress the compressed frame to produce required decompressed frames;
• supplying the required decompressed frames to the motion compensation engine;
• determining the predicted frame in the motion compensation engine;
• summing an output of the block decoder with an output of the motion compensation engine to obtain the decompressed frame;
• determining a speed and processing capacity of the processor;
• and
• by-passing portions of the block decoder and portions of the motion compensation engine responsive to the processor having a capacity and speed above that needed to operate the decoder in real time and perform the by-passed modules by the processor for the compressed frame.

A computer comprising:

• an input device;
• an output device;
• a processor;
• a memory;
• and,
• a decoder having:
• a parser, for parsing the compressed frame and separating motion compensation information and block data structures in the compressed frame having a first and second output;
• a block decoder for decoding pixels and interpicture prediction errors in the block data structures, having an input coupled to the first output of the parser having an IDCT module having an input coupled to the block array and an output coupled to the output of the block decoder;
• a motion compensation engine for obtaining a prediction macroblock using the motion compensation information, having an input coupled to the second output of the parser;
• a summing circuit for summing the decoded interpicture prediction errors and the prediction macroblock, having a first input coupled to an output of the decoder module and a second input coupled to an output of the motion compensation engine;
• wherein the processor includes information on the processors speed and capacity, and information on the memory available to the processor, the processor programmable to determine whether the capacity and speed of the processor are above that needed to operate the decoder in real time and perform the by-passed modules by the processor for the compressed frame;
• and
• a first connector for by-passing portions of the block decoder and portions of the motion compensation engine responsive to the capacity and speed of the processor being above that needed to operate the decoder in real time and perform the by-passed modules by the processor for the compressed frame.