Image sensor employing non-uniform A/D conversion

An image sensing device, comprising:

• an image sensor array having a plurality of imager cells arranged in at least one row and a plurality of columns, with an imager cell of any given column being coupled to a column data line of that column;
• analog to digital (A/D) conversion circuitry coupled to said column data lines, and operative to convert signals on said column data lines to digitized outputs at a varying resolution, said resolution being a function of signal amplitude;
• wherein said A/D conversion circuitry comprises:
• at least one comparator having a first input coupled to at least one of said column data lines, and a second input coupled to receive a time varying reference signal;
• an n-bit counter coupled to an output of said comparator;
• an n-bit main counter that counts in synchronism with said n-bit counter;
• an n-bit to m-bit converter coupled to receive an output of said n-bit main counter, where m>n, said converter nonlinearly converting n-bit codes of said main counter to m-bit codes;
• and
• an m-bit digital to analog (D/A) converter coupled to said n-bit to m-bit converter for converting said m-bit codes to said time-varying reference signal.

An image sensing device having correlated double sampling circuitry, said image device comprising:

• a plurality of imager cells arranged in rows and columns, with the imager cells of any given column being coupled to a column data line of that column, and each imager cell being operable to selectively provide a first signal on an associated column data line indicative of a reset level during a first sampling interval and to provide a second signal on the associated column data line during a second sampling interval indicative of an amount of light incident upon that imager cell;
• an n-bit unidirectional counter operative to count in one of an up or down direction during each of said first and second sampling intervals;
• an n-bit to m-bit converter coupled to receive an output of said n-bit main counter, where m>n, said n-bit to m-bit converter nonlinearly mapping an n-bit count of said main counter to an m-bit count;
• a digital to analog converter coupled to an output of said n-bit to m-bit converter, for converting the m-bit count to a reference signal that varies nonlinearly as a function of time, said reference signal varying nonlinearly during each of said first and second sampling intervals;
• a plurality of comparators, each having a first input coupled to an associated one of said column data lines for receiving said first and second signals in the first and second sampling intervals, respectively, and a second input coupled to receive said time varying reference signal;
• and
• a plurality of n-bit up/down counters, each operable to count in a first direction during said first sampling interval and in an opposite direction during said second sampling interval, each of said up/down counters being responsive to an output of one of said comparators to stop counting during each of the first and second sampling intervals when the amplitude of the time varying reference signal substantially equals the amplitude of the respective first or second signal, whereby each said up/down counter provides an output representing a subtraction of one of said first or second signals from the other to complete a correlated double sampling operation.

A non-uniform successive-approximation analog to digital (A/D) converter, comprising:

• a comparator for successively comparing an analog input signal with a changing reference signal;
• an n-bit successive approximation register that successively modifies an n-bit output code thereof in accordance with an output signal of said comparator until a least significant digit of said n-bit code is resolved;
• an n-bit to m-bit converter, where m>n, said n-bit to m-bit converter converting each n-bit code of said register to a corresponding m-bit code, said m-bit code being a nonlinear function of said n-bit code;
• and
• an m-bit digital to analog converter for converting said m-bit code of said n-bit to m-bit converter to said reference signal;
• whereby when said least significant bit is resolved, the n-bit code of said register represents a final approximation of said analog signal.