Phase locked loop including a sampling circuit for reducing spurious side bands

A phase locked loop, comprising:

• an oscillator for producing a variable frequency oscillator signal in response to a tuning signal;
• a difference circuit to receive a reference signal and said variable frequency oscillator signal and to produce a difference signal corresponding to an accumulation of phase differences of the reference signal and the variable frequency oscillator signal;
• and
• a sample circuit which samples the difference signal in response to a timing signal, and the timing signal repeatedly generated during a continuous accumulation of the phase differences to produce the tuning signal.

A frequency synthesizer, comprising:

• an oscillator comprising an input lead and an output lead, responsive to a tuning signal on said input lead to vary the frequency of an oscillator signal at the output lead;
• a divider comprising an input lead coupled to the output lead of the oscillator and an output lead, responsive to the oscillator signal at the divider input lead to generate a reduced frequency signal at the divider output lead;
• a difference circuit comprising a first input lead coupled to the output lead of the divider, a second input lead and an output lead, and said difference circuit responsive to the reduced frequency signal on the difference circuit first input lead and a reference signal on the difference circuit second input lead to generate a difference signal at the difference circuit output lead, and the difference signal corresponding to an accumulation of phase differences of the reference signal and the reduced frequency signal;
• and
• a sample circuit comprising a first input lead coupled to the output lead of the difference circuit, an output lead coupled to the input lead of the oscillator, and a second input lead responsive to a timing signal repeatedly generated during a continuous accumulation of the phase differences to sample the difference signal on the first input lead of the sample circuit and generate the tuning signal on the sample circuit output lead.

A phase locked loop, comprising:

• an oscillator comprising an input lead and an output lead, responsive to a tuning signal on said input lead to vary the frequency of an oscillator signal at the output lead;
• a difference circuit comprising a first input lead coupled to the output lead of the oscillator, a second input lead and an output lead, and said difference circuit responsive to the oscillator signal on the difference circuit first input lead and a reference signal on the difference circuit second input lead to generate a difference signal at the difference circuit output lead, and the difference signal corresponding to an accumulation of phase differences of the reference signal and the oscillator signal;
• and
• a sample circuit comprising a first input lead coupled to the output lead of the difference circuit, an output lead coupled to the input lead of the oscillator, and a second input lead responsive to a timing signal repeatedly generated during a continuous accumulation of the phase differences to sample the difference signal on the first input lead of the sample circuit and generate the tuning signal on the sample circuit output lead.

A method for operating a frequency synthesizer, comprising:

• generating an oscillator signal having a frequency corresponding to a tuning signal;
• dividing the oscillator signal by a division factor to generate a reduced frequency signal;
• combining a reference signal and the reduced frequency signal to generate a difference signal proportional to an accumulation of phase differences between the reference signal and the reduced frequency signal;
• and
• sampling the difference signal in response to a timing signal repeatedly generated during a continuous accumulation of the phase differences to produce the tuning signal.

A method for operating a phase locked loop, comprising:

• generating an oscillator signal having a frequency corresponding to a tuning signal;
• combining a reference signal and the oscillator signal to generate a difference signal proportional to an accumulation of phase differences between the reference signal and the oscillator signal;
• and
• sampling the difference signal in response to a timing signal repeatedly generated during a continuous accumulation of the phase differences to produce the tuning signal.

A difference circuit, comprising:

• a phase comparator to receive a first signal and a second signal to produce a phase difference signal corresponding to phase differences of the first and the second signal;
• and
• an integrator to continuously receive and integrate the phase difference signal to produce a difference signal corresponding to an accumulation of the phase differences of the first and the second signal;
• a sample circuit which samples the difference signal in response to a timing signal, and the timing signal repeatedly generated during a continuous accumulation of the phase differences;
• and
• a hold circuit to hold the sampled difference signal and produce a tuning signal, corresponding to the sampled difference signal.

A method for operating a difference circuit, comprising:

• combining a first signal and a second signal to generate a phase difference signal corresponding to phase differences of the first and the second signal;
• and
• integrating the phase difference signal to produce a difference signal corresponding to an accumulation of the phase differences of the first and the second signal;
• sampling the difference signal in response to a timing signal, and the timing signal repeatedly generated during a continuous accumulation of the phase differences;
• and
• holding the sampled difference signal;
• and generating a tuning signal, corresponding to the sampled difference signal.

A frequency synthesizer, comprising:

• an oscillator for producing a variable frequency oscillator signal in response to a tuning signal;
• a divider circuit which divides by a division factor and said divider circuit communicating with a reference signal source to receive a reference signal and to divide the reference signal by the division factor to produce a reduced frequency signal;
• a difference circuit to receive said variable frequency oscillator signal and to communicate with said divider circuit to receive said reduced frequency signal to produce a difference signal corresponding to an accumulation of phase differences of the variable frequency oscillator signal and the reduced frequency signal;
• and
• a sample circuit which samples the difference signal in response to a timing signal repeatedly generated during a continuous accumulation of the phase differences to produce the tuning signal.

A method for operating a frequency synthesizer, comprising:

• generating an oscillator signal having a frequency corresponding to a tuning signal;
• dividing a reference signal by a division factor to generate a reduced frequency signal;
• combining the oscillator signal and the reduced frequency signal to generate a difference signal proportional to an accumulation of phase differences between the oscillator signal and the reduced frequency signal;
• and
• sampling the difference signal in response to a timing signal repeatedly generated during a continuous accumulation of the phase differences to produce the tuning signal.

A frequency synthesizer, comprising:

• an oscillator for producing a variable frequency oscillator signal in response to a tuning signal;
• a divider circuit which divides by a division factor and communicating with said oscillator to receive and divide said variable frequency oscillator signal by the division factor to produce a reduced frequency signal;
• a difference circuit to receive a reference signal and said reduced frequency signal to produce a difference signal corresponding to a phase difference of the reference signal and the reduced frequency signal;
• and
• a sample circuit including an antisaturation circuit, and the antisaturation circuit to receive the difference signal, to detect a threshold condition on the difference signal, and to produce a lock signal, and said sample circuit sampling the difference signal in response to at least one of a timing signal and the lock signal to produce the tuning signal.

A phase locked loop, comprising:

• an oscillator for producing a variable frequency oscillator signal in response to a tuning signal;
• a difference circuit to receive a reference signal and said variable frequency oscillator signal to produce a difference signal corresponding to a cumulation of phase differences of the reference signal and the variable frequency oscillator signal;
• and
• a sample circuit including an antisaturation circuit, and the antisaturation circuit to receive the difference signal, to detect a threshold condition on said difference signal, and to produce a lock signal, and said sample circuit to sample the difference signal in response to at least one of a timing signal and the lock signal to produce the tuning signal.

A frequency synthesizer, comprising:

• an oscillator comprising an input lead and an output lead, responsive to a tuning signal on said input lead to vary the frequency of an oscillator signal at the output lead;
• a divider comprising an input lead coupled to the output lead of the oscillator and an output lead, responsive to the oscillator signal at the divider input lead to generate a reduced frequency signal at the divider output lead;
• a difference circuit comprising a first input lead coupled to the output lead of the divider, a second input lead and an output lead, and said difference circuit responsive to the reduced frequency signal on the difference circuit first input lead and a reference signal on the difference circuit second input lead to generate a difference signal at the difference circuit output lead, and the difference signal corresponding to a cumulation of phase differences of the reference signal and the reduced frequency signal;
• and
• a sample circuit including an antisaturation circuit, and the sample circuit comprising a first input lead and a second input lead, the first input lead being coupled to the output lead of the difference circuit, an output lead coupled to the input lead of the oscillator, and the antisaturation circuit comprising an input lead coupled to the first input lead of the sample circuit and an output lead coupled to the second input lead of the sample circuit, and responsive to a threshold condition on the difference signal on the input of the antisaturation circuit to generate a lock signal on the output of the antisaturation circuit, and the sample circuit responsive to at least one of a timing signal and the lock signal on the sample circuit second input lead, to sample the difference signal on the first input lead of the sample circuit and generate the tuning signal on the sample circuit output lead.

A method for operating a frequency synthesizer, comprising:

• generating an oscillator signal having a frequency corresponding to a tuning signal;
• dividing the oscillator signal by a division factor to generate a reduced frequency signal;
• combining a reference signal and the reduced frequency signal to generate a difference signal proportional to a cumulation of phase differences between the reference signal and the reduced frequency signal;
• detecting a threshold condition on the difference signal, and generating a lock signal;
• and
• sampling the difference signal in response to at least one of a timing signal and the lock signal to generate the tuning signal.

A method for operating a phase locked loop, comprising:

• generating an oscillator signal having a frequency corresponding to a tuning signal;
• combining a reference signal and the oscillator signal to generate a difference signal proportional to a cumulation of phase differences between the reference signal and the oscillator signal;
• detecting a threshold condition on the difference signal, and producing a lock signal;
• and
• sampling the difference signal in response to at least one of a timing signal and the lock signal to generate the tuning signal.

A frequency synthesizer, comprising:

• an oscillator for producing a variable frequency oscillator signal in response to a tuning signal;
• a divider circuit which divides by a division factor and said divider circuit communicating with a reference signal source to receive a reference signal and to divide the reference signal by the division factor to produce a reduced frequency signal;
• a difference circuit to receive said variable frequency oscillator signal and to communicate with said divider circuit to receive said reduced frequency signal to produce a difference signal corresponding to a cumulation of phase differences of the variable frequency oscillator signal and the reduced frequency signal;
• and
• a sample circuit which includes an antisaturation circuit, and the antisaturation circuit to receive the difference signal, to detect a threshold condition on said difference signal, and to produce a lock signal, and the sample circuit to sample the difference signal in response to at least one of a timing signal and the lock signal to produce the tuning signal.

A method for operating a frequency synthesizer, comprising:

• generating an oscillator signal having a frequency corresponding to a tuning signal;
• dividing a reference signal by a division factor to generate a reduced frequency signal;
• combining the oscillator signal and the reduced frequency signal to generate a difference signal proportional to a cumulation of phase differences between the oscillator signal and the reduced frequency signal;
• detecting a threshold condition on the difference signal, and generating a lock signal;
• and
• sampling the difference signal in response to at least one of a timing signal and the lock signal to generate the tuning signal.

A phase locked loop, comprising:

• an oscillator comprising an input lead and an output lead, responsive to a tuning signal on said input lead to vary the frequency of an oscillator signal at the output lead;
• a difference circuit comprising a first input lead coupled to the output lead of the oscillator, a second input lead and an output lead, and said difference circuit responsive to the oscillator signal on the difference circuit first input lead and a reference signal on the difference circuit second input lead to generate a difference signal at the difference circuit output lead, and the difference signal corresponding to an accumulation of phase differences of the reference signal and the oscillator signal;
• a sample circuit comprising a first input lead coupled to the output lead of the difference circuit, an output lead coupled to the input lead of the oscillator, and a second input lead responsive to a timing signal repeatedly generated during a continuous accumulation of the phase differences to sample the difference signal on the first input lead of the sample circuit and generate the tuning signal on the sample circuit output lead;
• and
• wherein said sample circuit further comprises:
• an antisaturation circuit comprising an input lead coupled to the first input lead of the sample circuit and an output lead coupled to the second input lead of the sample circuit, and responsive to a threshold condition on the difference signal on the input of the antisaturation circuit to generate a lock signal on the output of the antisaturation circuit;
• and
• said sample circuit second input lead is responsive to at least one of the timing signal and the lock signal on the sample circuit second input lead, to sample the difference signal on the first input lead of the sample circuit and generate the tuning signal on the sample circuit output lead.