Loading element for a logic gate

A direct coupled logic gate having an input stage comprising:

• first and second branch circuits each connected between a common power supply voltage source VDD and ground;
• the first branch circuit including a first, normally-OFF, FET switching transistor;
• the second branch circuit including a second, normally-OFF, FET switching transistor;
• the first and second FET switching transistors arranged in a common source configuration, and each having a respective gate terminal for receiving a corresponding one of a pair of input logic signals;
• a first loading element disposed in the first branch circuit between VDD and the first FET switching transistor;
• and
• a second loading element disposed in the second branch circuit between VDD and the second FET switching transistor;
• wherein each loading element includes at least one resistive element and at least one voltage limiting element connected in parallel with one another.