Loading patent…
AssigneeTokyo Electron Limited
InventorsAkira Koshiishi, Masahiro Ogasawara, Keizo Hirose, Kazuya Nagaseki, Riki Tomoyoshi, Makoto Aoki
Estimating the term…
A lower insulating member 13 is arranged around a suscepter 6 as a lower electrode, and an upper insulating member 31 is arranged around an upper electrode 21. An outer end portion 31a of the upper insulating member is positioned outside an lower insulating member 13, to be lower than the upper surface of a wafer W. The narrowest distance between the lower insulating member 13 and the upper insulating member 31 is arranged to be smaller than a gap G between electrodes. Diffusion of a plasma generated between electrodes is restricted and prevented from spreading to the sides, so that inner walls of a processing container 3 are not sputtered.
A plasma processing apparatus wherein upper and lower electrodes are arranged opposite to each other in a processing chamber whose pressure can be freely reduced, a plasma is generated between the upper and lower electrodes by supplying a high frequency power, and processing is performed on a substrate to be processed which is mounted on the lower electrode, wherein
A plasma processing apparatus wherein upper and lower electrodes are arranged opposite to each other in a processing chamber whose pressure can be freely reduced, a plasma is generated between the upper and lower electrodes by supplying a high frequency power, and processing is performed on a substrate to be processed which is mounted on the lower electrode, wherein
A plasma processing apparatus wherein upper and lower electrodes are arranged opposite to each other in a processing chamber whose pressure can be freely reduced, a plasma is generated between the upper and lower electrodes by supplying a high frequency power, and processing is performed on a substrate to be processed which is mounted on the lower electrode, wherein
Dependencies are inferred from the claim text.