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US 5,915,190 AGranted
Methods for filling trenches in a semiconductor wafer
AssigneeLam Research Corporation
InventorDavid R. Pirkle
Life of this patent
Estimating the term…
Abstract
A method for filling a trench in a semiconductor wafer that is disposed in a plasma-enhanced chemical vapor deposition chamber. The method includes the step of depositing a protection layer of silicon dioxide over the wafer and into the trench while the wafer is biased at a first RF bias level. The protection layer has a thickness that is insufficient to completely fill the trench. Further, there is provided the step of forming a trench-fill layer of silicon dioxide over the protection layer and into the trench while the wafer is biased at a second RF bias level that is higher than the first bias level.
Claims18
In a plasma-enhanced chemical vapor deposition chamber, a method for filling a trench of a semiconductor device, comprising:
- depositing a protection layer of silicon dioxide over a wafer, said wafer being employed for fabricating said semiconductor device, and into said trench while said wafer is biased at a first RF bias level, said protection layer having a thickness that is insufficient to completely fill said trench;
- and
- depositing a trench-fill layer of silicon dioxide trench-fill material over said protection layer and into said trench while said wafer is biased at a second RF bias level that is higher than said first RF bias level to substantially fill said trench with said trench-fill material, wherein said protection layer is deposited at a first rate and said trench-fill layer is deposited at a second rate higher than said first rate, and wherein said second RF bias level causes sputtering, thereby causing said trench-fill material to be simultaneously sputtered and deposited over said protection layer and into said trench during said step of depositing said trench-fill layer.
A method for manufacturing an integrated circuit, comprising:
- providing a semiconductor wafer having a trench;
- filling said trench by:
- depositing a protection layer of silicon dioxide over a wafer, said wafer being employed for fabricating said semiconductor device, and into said trench while said wafer is biased at a first RF bias level, said protection layer having a thickness that is insufficient to completely fill said trench, and
- depositing a trench-fill layer of silicon dioxide trench-fill material over said protection layer and into said trench while said wafer is biased at a second RF bias level that is higher than said first RF bias level to substantially fill said trench with said trench fill material, wherein said protection layer is deposited at a first rate and said trench-fill layer is deposited at a second rate higher than said first rate and wherein said second RF bias level causes sputtering, thereby causing said trench-fill material to be simultaneously sputtered and deposited over said protection layer and into said trench during said step of depositing said trench-fill layer.
1 more element
A method for manufacturing an integrated circuit, comprising:
- providing a semiconductor wafer having a trench;
- filling said trench by:
- depositing a protection layer of silicon dioxide over a wafer, said wafer being employed for fabricating said semiconductor device, and into said trench while said wafer is biased at a first RF bias level, said protection layer having a thickness that is insufficient to completely fill said trench, and
- depositing a trench-fill layer of silicon dioxide trench-fill material over said protection layer and into said trench while said wafer is biased at a second RF bias level that is higher than said first RF bias level to substantially fill said trench with said trench fill material, wherein said protection layer is deposited at a first rate and said trench-fill layer is deposited at a second rate higher than said first rate and wherein a flow rate of a silicon-bearing source gas during said depositing said protection layer step is lower than a flow rate of said silicon-bearing source gas during said depositing said trench-fill layer step to compensate for a sputtering action during said depositing said trench-fill layer step, thereby improving a trench fill rate during said depositing said trench-fill layer step.
1 more element
A method for manufacturing an integrated circuit, comprising:
- providing a semiconductor wafer having a trench;
- filling said trench by:
- depositing a protection layer of silicon dioxide over a wafer, said wafer being employed for fabricating said semiconductor device, and into said trench while said wafer is biased at a first RF bias level, said protection layer having a thickness that is insufficient to completely fill said trench, and
- depositing a trench-fill layer of silicon dioxide trench-fill material over said protection layer and into said trench while said wafer is biased at a second RF bias level that is higher than said first RF bias level to substantially fill said trench with said trench fill material, wherein said protection layer is deposited at a first rate and said trench-fill layer is deposited at a second rate higher than said first rate and wherein said trench is employed to electrically isolate adjacent transistors from one another.
1 more element
In a plasma-enhanced chemical vapor deposition chamber, a method for filling a trench of a semiconductor device, comprising:
- depositing a protection layer of silicon dioxide over a wafer, said wafer being employed for fabricating said semiconductor device, and into said trench while said wafer is biased at a first RF bias level, said protection layer having a thickness that is insufficient to completely fill said trench;
- and
- depositing a trench-fill layer of silicon dioxide trench-fill material over said protection layer and into said trench while said wafer is biased at a second RF bias level that is higher than said first RF bias level to substantially fill said trench with said trench-fill material, wherein said protection layer is deposited at a first rate and said trench-fill layer is deposited at a second rate higher than said first rate, a flow rate of a silicon-bearing source gas during said depositing said protection layer step is lower than a flow rate of said silicon-bearing source gas during said depositing said trench-fill layer step to compensate for a sputtering action during said depositing said trench-fill layer step, thereby improving a trench fill rate during said depositing said trench-fill layer step.
In a plasma-enhanced chemical vapor deposition chamber, a method for filling a trench of a semiconductor device, comprising:
- depositing a protection layer of silicon dioxide over a wafer, said wafer being employed for fabricating said semiconductor device, and into said trench while said wafer is biased at a first RF bias level, said protection layer having a thickness that is insufficient to completely fill said trench;
- and
- depositing a trench-fill layer of silicon dioxide trench-fill material over said protection layer and into said trench while said wafer is biased at a second RF bias level that is higher than said first RF bias level to substantially fill said trench with said trench-fill material, wherein said protection layer is deposited at a first rate and said trench-fill layer is deposited at a second rate higher than said first rate, said trench is employed to electrically isolate adjacent transistors from one another.
Dependencies are inferred from the claim text.