Field programmable memory array

A programmable memory array having a plurality of memory cells arranged in rows and columns, a row of cells having an associated word line, and a column of cells having associated therewith a programmable bit line structure, said programmable bit line structure of the column of cells comprising:

• a plurality of local bit lines, each local bit line of said plurality of local lines being associated with a respective sub-array group of memory cells of said given column of cells;
• and
• a local selective coupler between adjacent local bit lines of said plurality of local bit lines, said selective coupler being programmable for selectively propagating a signal there between;
• a plurality of semi-global bit lines, each semi-global bit line of said plurality of semi-global bit lines being associated with respective segments of memory cells of said column, each segment encompassing a plurality of said sub-array groups of memory cells;
• and
• a semi-global selective coupler between adjacent semi-global bit lines of said plurality of semi-global bit lines, said semi-global selective coupler being programmable for selectively propagating a signal there between;
• and
• a first hierarchical selective switch between each local bit line of a given sub-array group of memory cells and the associated semi-global bit line of the segment encompassing said given sub-array group, each first hierarchical selective switch being programmable for selectively propagating a signal between said associated local bit line and the respective semi-global bit line.

A programmable memory array comprising:

• a plurality of memory sub-arrays, each memory sub-array including a plurality of memory cells arranged in rows and columns, a plurality of local bit lines wherein each column of memory cells has an associated local bit line of said plurality of local bit lines for presenting/receiving data to/from the memory cells thereof, and a plurality of word lines wherein each row of said plurality of memory cells has an associated word line providing a select signal for controlling access of the memory cells of said row to associated local bit lines;
• and
• a programmable bus matrix for selectively configuring local bit lines of the various memory sub-arrays;
• said programmable bus matrix being programmable in a first configuration wherein the local bit lines of one sub-array of said plurality of sub-arrays are electrically intercoupled to corresponding local bit lines of another sub-array of said plurality of sub-arrays so as to provide common bit lines for the respective memory cells of the corresponding columns of said one and said another sub-arrays;
• and
• said programmable bus matrix being programmable in a second configuration wherein the local bit lines of said one sub-array of said plurality of sub-arrays are electrically configured in parallel with corresponding local bit lines of said another sub-array of said plurality of sub-arrays so as to provide separate, parallel bit lines for accessing the memory cells of the corresponding columns of said one and said another sub-arrays.

A memory array comprising:

• Z memory blocks, each of said memory blocks comprising a generally rectangular sub-array of M.times.N memory cells;
• address lines connectable to each of said memory blocks;
• data lines connectable to each of said memory blocks;
• I/O circuitry;
• and
• programming elements distributed within said address lines, data lines, and I/O circuitry such that at least one portion of said z memory blocks can be configured into an iM.times.jN memory, wherein i and j are positive integers, by programming said programming elements.