FPGA repeatable interconnect structure with hierarchical interconnect lines

An FPGA comprising:

• an array of tiles, each tile including:
• a logic block;
• a plurality of PIPs;
• a plurality of line segments, each such line segment abutting another such line segment in an adjacent such tile to form a plurality of interconnect lines;
• some of said interconnect lines being single-length lines programmably connecting two such logic blocks in two adjacent such tiles;
• some other of said interconnect lines being intermediate-length lines, said intermediate-length lines not connecting any two tiles connected by one of said single-length lines, one of said intermediate-length lines programmably connecting a first such logic block in a first such tile to a second such logic block in a second such tile, said second tile being separated from said first tile by a first number of such tiles, and further programmably connecting said first logic block in said first tile to a third such logic block in a third such tile, said third tile being separated from said first tile by a second number of such tiles;
• said first number is at least one;
• and
• said second number is at least three.

An interconnect structure for interconnecting logic blocks in an FPGA, comprising:

• an array of logic blocks arranged in rows and columns, said logic blocks each having inputs and outputs;
• a plurality of interconnect lines comprising a plurality of single-length lines and a plurality of intermediate-length lines,
• each such single-length line being of sufficient length to connect to said inputs and outputs of two such adjacent logic blocks;
• and
• each such intermediate-length line being of sufficient length to connect to said outputs of three such logic blocks separated from each other by at least one such logic block, each such intermediate-length line unconnectable to outputs of any two adjacent logic blocks;
• and
• a plurality of PIPs, each such PIP programmably connecting one of said interconnect lines to another of said interconnect lines.

An FPGA having a plurality of adjacent tiles arranged in a rectangular array, each such tile having four edges, each such tile comprising:

• a logic block having input lines and at least one output line;
• a plurality of interconnect line segments comprising a plurality of single-length line segments and a plurality of intermediate-length line segments, at least some of said single-length line segments comprising at least some of said logic block input lines, wherein:
• each such single-length line segment extends to one such edge of said tile and connects to a single-length line segment in an adjacent such tile, thereby forming a single-length line;
• said plurality of intermediate-length line segments comprise end segments and interior segments, wherein:
• each such interior segment extends from one such edge of said tile to an opposite such edge of said tile and is laid out with an offset such that a connection is made to a different interior segment in an adjacent such tile, thereby forming a continuous intermediate-length line;
• each such end segment has first and second ends, said first end extending to one such edge of said tile such that a connection is made to an interior segment in an adjacent such tile, said second end terminating within said tile;
• and
• a plurality of PIPs comprising interconnect PIPs and output PIPs, each such interconnect PIP programmably connecting one of said interconnect line segments to another of said interconnect line segments, and each such output PIP programmably connecting one of said interconnect line segments to one of said at least one logic block output line;
• wherein some of said of said interior segments do not connect to any of said PIPs.

An FPGA comprising:

• a plurality of logic blocks having inputs and outputs;
• a plurality of interconnect lines of at least two lengths including shorter lines and longer lines;
• and
• a plurality of PIPs for connecting said interconnect lines to each other, to said logic block inputs, and to said logic block outputs;
• said PIPs being placed such that
• said logic block outputs are connectable to said shorter lines and further connectable to said longer lines without traversing one of said shorter lines, and
• said logic block inputs are connectable to said shorter lines, and not connectable to said longer lines without traversing one of said shorter lines.

An FPGA comprising:

• an array of tiles, each tile including:
• a logic block;
• and
• a plurality of line segments, each such line segment abutting another such line segment in an adjacent such tile to form a plurality of interconnect lines;
• and wherein:
• some of said interconnect lines are single-length lines programmably connecting two such logic blocks in two adjacent such tiles;
• some other of said interconnect lines are intermediate-length lines, said intermediate-length lines not connecting any two tiles connected by said single-length lines, one of said intermediate-length lines programmably connecting one such logic block in one such tile to another such logic block in another such tile separated from said one tile by a first number of such tiles, and further programmably connecting one such logic block in said one tile to other such logic blocks in other such tiles separated from said one tile by a second number of such tiles;
• said first number is at least one;
• and
• said second number is at least three.

An interconnect structure for interconnecting an array of logic blocks, comprising:

• an interconnect line;
• at least five logic blocks arranged sequentially along said interconnect line;
• and
• at least three PIPs for connecting said interconnect line to said logic blocks;
• said PIPs being located so as to leave at least one logic block unconnectable to said interconnect line between each pair of logic blocks connectable to said interconnect line.

An FPGA comprising:

• an array of tiles, each tile including:
• a logic block;
• a plurality of PIPS;
• and
• a plurality of line segments, each such line segment abutting another such line segment in an adjacent such tile to form a plurality of interconnect lines for programmably connecting such logic blocks to each other, some of said interconnect lines being long lines programmably connecting at least two such logic blocks in at least two such tiles separated from each other by at least one such tile;
• wherein:
• at least one of said long lines is connected to some of said logic blocks through some of said PIPs in a pattern that repeats along the length of said one long line, said pattern spanning at least two tiles.

An FPGA comprising:

• an array of tiles, each tile including:
• a logic block;
• a plurality of PIPs;
• and
• a plurality of line segments, each such line segment abutting another such line segment in an adjacent such tile to form a plurality of interconnect lines for programmably connecting such logic blocks to each other, some of said interconnect lines being long lines programmably connecting at least two such logic blocks in at least two such tiles separated from each other by at least one such tile;
• wherein:
• at least one of said long lines is connected to others of said interconnect lines through some of said PIPs in a pattern that repeats along the length of said one long line, said pattern spanning at least two tiles.