Process flow design at the module effects level through the use of acceptability regions

A method for designing a semiconductor manufacturing process flow for a manufacturable device comprising the steps of:

• a. partitioning of said semiconductor manufacturing process flow into a number of abstraction levels having at least a device performance level for describing device performance specifications, a device designables level having device state specifications for describing features of a device that can be modified to obtain the desired performance, and a module effects level;
• b. translating device performance specifications from the device performance level to device state specifications at the device designables level;
• c. translating between said device designables level and said module effects level by a sequence comprising the steps of:
• i. identifying sequences of processes that can be grouped together to form at least two modules where each module of processes has outgoing wafer states and incoming wafer states, and where at least two modules is a sequence of modules which has at least a first module and a final module;
• ii. describing module models for each module as acceptability regions of constraints at the module effects level of abstraction which specify the set of said outgoing wafer states possible for said incoming wafer states;
• and
• iii. propagating constraints of said final module backwards toward said first module by intersecting said final module constraints with successively earlier module constraints in said sequence of modules.

A computer system for designing a semiconductor manufacturing process flow for a semiconductor device comprising the steps of:

• a. means for partitioning of said semiconductor manufacturing process flow into a number of abstraction levels having at least a device performance level for describing device performance specifications, a device designables level having device state specifications for describing features of a device that can be modified to obtain the desired performance, and a module effects level;
• b. means for translating device performance specifications from the device performance level to device state specifications at the device designables level, while allowing the user to select specific device performance constraints in said device performance level;
• c. means for translating between said device designables level and said module effects level by a sequence comprising the steps of:
• i. identifying sequences of processes that can be grouped together to form at least two modules where each module of processes has outgoing wafer states and incoming wafer states, and where at least two modules is a sequence of modules which has at least a first module and a final module;
• ii. describing module models for each module as acceptability regions of constraints at the module effects level of abstraction which specify the set of said outgoing wafer states possible for said incoming wafer states;
• and
• iii. propagating constraints of said final module backwards toward said first module by intersecting said final module constraints with successively earlier module constraints in said sequence of modules.