Circuit design methods and tools
AssigneeViewlogic Systems, Inc.
InventorDavid L. Johannsen
Life of this patent
Estimating the term…
Abstract
A circuit design tool which includes (1) separating structural and functional aspects of components, so as to specify the desired functional behaviour of the component, leaving the actual gate-level design of the component to the design tool; (2) translating a model of the desired logical behaviour of a circuit into a regularized set of functional components to achieve that desired behaviour; (3) verifying structural equivalence between pairs of components; (4) a method for bit-reversing the signal flow in a component; (5) a method for performing arithmetic operations backwards from a natural order; (6) an architecture for a multiplier which is faster and more compact than known multipliers; and (7) a method of translating a logic equation into a netlist of connected logic gates.
Claims15
A method for bit-reversing signal flow in the operation of a circuit design tool, said method comprising the steps of:
- receiving a first description of a component structure having a set of bitslices, each one of said set of bitslices having a logic block, and each one of said set of bitslices operating on an input bit, producing an output bit, having a carry signal input and a carry signal output, wherein a carry signal output corresponding to a selected one of said set of bitslices is coupled to a carry signal input of a next one of said set of bitslices, said carry signal output being responsive to said carry signal input, said carry signals having a directional signal flow;
- replacing each one of said set of bitslices with a first carry-logic block and a second logic block representing behavioral characteristics of said one of said set of bitslices;
- replacing carry-logic blocks coupled in series with a merge-carry block;
- constructing a logical truth table in response to said replacing steps;
- combining said second logic block with said merge-carry block using said logical truth table;
- and
- constructing a functional description for each said second logic block.
A method for verifying structural equivalence of a first circuit structure and a second circuit structure in the operation of a circuit design tool, said method comprising the steps of:
- receiving a description of the first circuit structure and a description of the second circuit structure;
- verifying that for each port/pin in said first description there is an equivalent port/pin in said second description;
- verifying that for each port/pin in said second description there is an equivalent port/pin in said first description;
- removing each delay gate and each time gate from said first structural description;
- removing each delay gate and each time gate from said second structural description;
- wherein each said delay gate includes an input and an output, said delay gate passing said input through to said output after a delay of one clock cycle, and
- wherein each said time gate includes an input, an output, and a designated clock cycle, wherein said in put is passed through to said output in said designated clock cycle;
- applying a set of replacement rules to said first structural description and said second structural description;
- and
- verifying equivalence of said first and second structural descriptions resulting from said applying step.
A method according to claim 19, both of said removing steps further comprising the sub-steps of:
- determining a number T of used clock cycles;
- constructing T copies of said structural description;
- coupling input and output bits for each one of said T clock cycles to corresponding copies of said structural description;
- replacing each time gate within each one of said T copies of said structural description with a connection from its clock cycle t to a next clock cycle t+1;
- and
- removing each unused logic block from each one of said T copies of said structural description, wherein each logic block comprises a set of input values, a set of output values, and is associated with a logic equation used to generate said set of output values from said set of input values.
Dependencies are inferred from the claim text.