Multi-port ethernet frame switch

A network switch, comprising:

• (a) a plurality of media access control (MAC) interface logic circuits each coupled to an associated output port operative to perform serializer/deserializer conversion and to transfer incoming frames to an external memory, and to transfer outgoing frames from the external memory to their destination, said frames being transferred one at a time;
• (b) an internal bus;
• (c) a buffer memory coupled to each of said MAC interface logic circuits at one end and to said internal bus at another end;
• (d) a switch central processor coupled to said internal bus, said switch central processor having firmware operative to perform frame address handling and control transfer of incoming frames to their destinations, to implement statistics counter maintenance for remote monitoring, collision back-off time computation, frame enqueuing and dequeuing, buffer deallocation, error processing and MAC protocol functions;
• (e) a multi-channel Direct Memory Access (DMA) controller coupled to said internal bus and to said switch central processor, operative to transfer incoming frames to the external frame memory and to transfer outgoing frames stored temporarily in the external frame memory to their destination, said outgoing frames being transferred one at a time in accordance with instructions from said switch central processor;
• (f) an external frame memory controller coupled to an external frame memory port;
• wherein said switch central processor has queuing firmware operative to set up transmit and receive queuing functions for frame transfer to and from said frame memory and storage in said frame memory.

A plurality of network switches, each of said plurality of network switches comprising:

• (a) a plurality of media access control (MAC) interface logic circuits each coupled to an associated output port operative to perform clock synchronization, preamble generation, and stripping and data buffering required to convert between bit-serial data streams exchanged with external transceivers and parallel data streams employed internally by said network switch;
• (b) an internal bus;
• (c) a switch central processor coupled to said internal bus;
• (d) a multi-channel Direct Memory Access (DMA) controller coupled to said internal bus and to said switch central processor, operative to transfer incoming frames to an external memory and to transfer outgoing frames stored temporarily in the external memory to their destination, said outgoing frames being transferred one at a time in accordance with instructions from said switch central processor;
• (e) a memory controller coupled to said DMA controller and to an external memory port operative to interface between said DMA controller and the external memory;
• and
• (f) an expansion bus interface logic circuit coupled to said DMA Controller and to an expansion bus port;
• wherein said switch central processor performs frame address handling and controls transfer of incoming frames to their destination, and wherein said switch central processor has queuing firmware operative to set up transmit and receive queuing functions for frame transfer to and from the frame memory and storage in the frame memory and expansion bus coupled to said expansion bus interface logic circuit of each of said plurality of network switches.