Refresh sampling built-in self test and repair circuit

A system for detecting data retention faults, wherein the system comprises:

• a memory array including a plurality of memory cells;
• a testing unit coupled to the memory array, and configured to determine the failure times for a first subset of said plurality of memory cells;
• and
• a parameter calculation unit coupled to receive said failure times, and configured to determine a first refresh pause time based on said failure times;
• wherein said testing unit is further coupled to receive the first refresh pause time, and further configured to detect faulty cells among said plurality of memory cells by performing a data retention test using said refresh pause time.

A memory device comprising:

• a plurality of memory cells;
• a data line;
• a first weak write circuit coupled to said data line and one or more cells of said plurality of memory cells, wherein said first weak write circuit includes:
• a first gating device coupled to said data line and said one or more cells;
• a resistive device coupled to said data line;
• a second gating device coupled to said resistive device and said one or more cells;
• and
• a weak enable line coupled to a first control input of said first gating device and to a second control input of said second gating device;
• wherein said first gating device is configured to couple said data line to said one or more cells when a first logical value is asserted on said weak enable line;
• wherein said second gating device is configured to decouple said resistive device from said one or more cells when said first logical value is asserted on said weak enable line;
• wherein said first gating device is configured to decouple said data line from said one or more cells when a second logical value is asserted on said weak enable line;
• and
• wherein said second gating device is configured to couple said resistive device to said one or more cells when said second logical value is asserted on said weak enable line;
• wherein said second logical value is the complement of said first logical value.