US 5,909,136 AGranted

Quarter-square multiplier based on the dynamic bias current technique

AssigneeNEC Corporation

InventorKatsuji Kimura

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Abstract

A four-quadrant multiplier which is constructed from two squaring circuits using the quarter-square technique and is suitable for an integrated circuit (IC) or a large-scale integrated circuit (LSI). Each of the squaring circuits has a pair of differential input terminals, an output terminal and two differential pairs. Each of differential pairs is composed of first and second transistors whose sources or emitters are connected in common, receives a differential input voltage impressed between the differential input terminals. In each differential pair, a constant current source of a predetermined current value and an dynamic bias current source are inserted in parallel between the common sources or the common emitters and the grounding point. The dynamic bias current source is realized by a current mirror circuit which outputs current equal to the drain current or the collector current of the second transistor. Therefore, the tail current of each differential pair is current given by the sum of the output current of the second transistor and the predetermined constant current. The output current of each squaring circuit is represented by the sum of the drain currents or the collector currents of the second transistors of both of the differential pairs.

Claims9

Dependent claims

A four-quadrant multiplier that inputs a first signal voltage and a second signal voltage, said second signal voltage being composed of a non-inverted voltage and an inverted voltage, and that outputs a differential current that corresponds to a product of said first signal voltage and said second signal voltage, said multiplier comprising:

a pair of squaring circuits, each of said squaring circuits having a pair of differential input terminals and outputting current based on differential voltage impressed between said differential input terminals,
wherein one of said squaring circuits takes as differential inputs said first signal voltage and said inverted voltage, the other squaring circuit takes as differential inputs said first signal voltage and said non-inverted voltage, and said differential current is the difference between current outputted by said first squaring circuit and current outputted by said second squaring circuit;
a first differential pair in each of said squaring circuits having a first transistor and a second transistor;
and
a second differential pair in each of said squaring circuits having a third transistor and a fourth transistor, and
wherein, in each of said squaring circuits which uses a dynamic biasing technique and having a current feedback factor of not less than one, said first differential pair operating in a saturation region is driven by a first tail current which is controlled to equal a sum of one of drain and collector currents of said second transistor and constant current of a predetermined value, where when said second transistor is an MOS transistor then said drain current of said second transistor I.sub.D2 is governed by:
##EQU11## where .beta. is the transconductance parameter, V.sub.i is a voltage impressed between the gates of two transistors making up the first differential pair, and I.sub.O is a constant current, and when said second transistor is a bipolar transistor then said collector current of said second transistor I.sub.C2 is governed by:
I.sub.C2 =I.sub.O exp(-V.sub.i /V.sub.T)
where V.sub.i is a voltage impressed between the bases of two transistors making up the first differential pair, V.sub.T is the thermal voltage, and I.sub.O is a constant current and said second differential pair operating in a saturation region is driven by a second tail current which is controlled to equal a sum of one of drain and collector currents of said third transistor and constant current of said predetermined value, and current outputted by each of said squaring circuits is given by a sum of current outputted by said second transistor and current outputted by said third transistor.

6 more elements

a pair of squaring circuits, each of said squaring circuits having a pair of differential input terminals and outputting current based on differential voltage impressed between said differential input terminals,
wherein one of said squaring circuits takes as differential inputs said first signal voltage and said inverted voltage, the other squaring circuit takes as differential inputs said first signal voltage and said non-inverted voltage, and said differential current is the difference between current outputted by said first squaring circuit and current outputted by said second squaring circuit;
and
each of said squaring circuits comprises:
a first differential pair composed of a first MOS transistor and a second MOS transistor, wherein a source of said first MOS transistor is commonly connected to a source of said second MOS transistor;
a second differential pair composed of a third MOS transistor and a fourth MOS transistor, wherein a source of said third MOS transistor is commonly connected to a source of said fourth MOS transistor;
a first constant-current source inserted between a grounding point and said sources of said first and second MOS transistors;
a second constant-current source having a same current value as that of said first constant-current source inserted between said grounding point and said sources of said third and fourth MOS transistors;
a first current mirror circuit that is connected to a drain of said second MOS transistor and outputting current which mirrors a drain current of said second MOS transistor;
a second current mirror circuit that is connected to a drain of said third MOS transistor outputting current which mirrors a drain current of said third MOS transistor;
a third current mirror circuit receiving said current of said first current mirror circuit and having an output transistor inserted between said grounding point and said sources of said first and second MOS transistors of said first differential pair;
and
a fourth current mirror circuit receiving said current of said second current mirror circuit and having an output transistor inserted between said grounding point and said sources of said third and fourth MOS transistors of said second differential pair,
wherein, in each of said squaring circuits which uses a dynamic biasing technique and having a current feedback factor of not less than one, said first differential pair operating in a strong inversion region is driven by a first tail current given by a sum of drain current of said second transistor I.sub.D2 and constant current of a predetermined value, where said drain current of said second transistor is governed by:
##EQU12## where .beta. is the transconductance parameter, V.sub.i is a voltage impressed between the gates of two transistors making up the first differential pair, and I.sub.O is a constant current and said second differential pair operating in a strong inversion region is driven by a second tail current given by a sum of drain current of said third transistor and constant current of said predetermined value, and
wherein gates of said first and third MOS transistors in each of said squaring circuits are connected to one of said differential input terminals, gates of said second and fourth MOS transistors are connected to the other of said differential input terminals, and the output current of each of said squaring circuits is equivalent to a sum of drain current of said second MOS transistor and drain current of said third MOS transistor.

13 more elements

a pair of squaring circuits, each of said squaring circuits having a pair of differential input terminals and outputting current based on differential voltage impressed between said differential input terminals,
wherein one of said squaring circuits takes as differential inputs said first signal voltage and said inverted voltage, the other squaring circuit takes as differential inputs said first signal voltage and said non-inverted voltage, and said differential current is the difference between current outputted by said first squaring circuit and current outputted by said second squaring circuit;
and each of said squaring circuits comprises:
a first differential pair composed of a first bipolar transistor and a second bipolar transistor, wherein an emitter of said first bipolar transistor is commonly connected to an emitter of said second bipolar transistor;
a second differential pair composed of a third bipolar transistor and a fourth bipolar transistor, wherein an emitter of said third bipolar transistor is commonly connected to an emitter of said fourth bipolar transistor;
a first constant-current source inserted between a grounding point and said emitters of said first and second bipolar transistors;
a second constant-current source having a same current value as that of said first constant-current source inserted between said grounding point and said emitters of said third and fourth bipolar transistors;
a first current mirror circuit that is connected to a collector of said second bipolar transistor outputting current which mirrors a collector current of said second bipolar transistor;
a second current mirror circuit that is connected to a collector of said third bipolar transistor outputting current which mirrors a collector current of said third bipolar transistor;
a third current mirror circuit receiving said current of said first current mirror circuit and having an output transistor inserted between said grounding point and said emitters of said first and second bipolar transistors of said first differential pair;
and
a fourth current mirror circuit receiving said current of said second current mirror circuit and having an output transistor inserted between said grounding point and said emitters of said third and fourth bipolar transistors of said second differential pair,
wherein, in each of said squaring circuits which uses a dynamic biasing technique and having a current feedback factor of not less than one, said first differential pair operating in a saturation region is driven by a first tail current given by a sum of collector current of said second transistor I.sub.C2 and constant current of a predetermined value, where said collector current of said second transistor is governed by:
I.sub.C2 =I.sub.O exp(-V.sub.i /V.sub.T)
where V.sub.i is a voltage impressed between the bases of two transistors making up the first differential pair, V.sub.T is the thermal voltage, and I.sub.O is a constant current and said second differential pair operating in a saturation region is driven by a second tail current given by a sum of collector current of said third transistor and constant current of said predetermined value, and
wherein bases of said first and third bipolar transistors in each of said squaring circuits are connected to one of said differential input terminals, bases of said second and fourth bipolar transistors are connected to the other of said differential input terminals, and the output current of each of said squaring circuits is equivalent to a sum of collector current of said second bipolar transistor and collector current of said third bipolar transistor.

13 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/928,452Filed 12 Sep 1997 · continuation
Priority: JP 6-2014853 Aug 1994
Granted: 1 Jun 1999
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

G06G 7/164
For multiplication or division: using means for evaluating powers, e.g. quarter square multiplier
H03F 3/45085
Using bipolar transistors as the active amplifying circuit: long tailed pairs
H03F 3/45183
Using MOSFET transistors as the active amplifying circuit: long tailed pairs
H03F 3/4521
Using MOSFET transistors as the active amplifying circuit: complementary long tailed pairs having parallel inputs and being supplied in parallel