Circuits with dynamically biased active loads

A logic gate comprising:

• a plurality of active loads;
• and
• a plurality of time-delayed negative feedback bias circuits, each of the bias circuits is coupled to a different one of said active loads, the logic gate having a plurality of logic gate inputs adapted to receive an external input signal and a plurality of logic gate outputs, at least one of said logic gate outputs being adapted to transmit an output signal externally, each of said active loads having no resistors and serving as a load to a different one of said logic gate outputs, and each said logic gate output having an output signal being a single inversion of the external input signal at said logic gate input and being delayed from the external signal by a propagation delay resulting from a single active component, and wherein
• said bias circuit dynamically biasing said active load such that said active load presents an effective load that varies according to a logic state of said logic gate output, and wherein
• an output signal at said at least one of said logic gate outputs swings substantially from 1.1 to 1.4 volts, when the device is energized from a voltage source of 1.4 volts and the external input signal swings substantially from 1.4 to 1.1.

A method for dynamically biasing each of a plurality of active loads within a device, said method comprising the steps of:

• providing each of said active loads with a load input and a load output, said active loads being resistorless, said load output being coupled to a circuit output of said device, said circuit output being adapted to transmit an output signal externally, and having a signal with a signal level;
• sensing said signal;
• amplifying said signal level with a gain of less than unity;
• delaying said signal to form a delayed output;
• and
• feeding said delayed output to said load input to provide negative feedback to said at least one active load, and wherein
• an output signal at the circuit output swings substantially from 1.1 to 1.4 volts, when the device is energized from a voltage source of 1.4 volts and a device input signal swings substantially from 1.4 to 1.1.

A device comprising:

• a plurality of transistors,
• at least one input circuit element, each circuit element consisting of one of said transistors and having at least one device input adapted for receiving an external input signal and at least one device output adapted to provide an output signal, said device output having an output signal being a single inversion of the external input signal,
• each circuit element having:
• an active load coupled to said at least one device output, said active load having a load input, and
• an output sensing circuit having a sensing input coupled to said at least one device output, a sensing output coupled to said load input, a voltage gain less than unity and a delay, said sensing circuit providing negative feedback to said active load, and wherein
• an output signal at said at least one device output swings substantially from 1.1 to 1.4 volts, when the device is energized from a voltage source of 1.4 volts and a signal at said at least one device input swings substantially from 1.4 to 1.1.

A logical gate comprising:

• a plurality of transistors;
• at least one of said transistors having a first transistor node being a gate input node adapted to receive an external signal and a second transistor node being a gate output node, each gate output node having an active load, said active load having a load input;
• at least one output sensing circuit having a sensing input, a sensing output, a voltage gain less than unity and a delay, the sensing input being coupled to said at least one gate output, a sensing output coupled to said load input, node coupled to said gate output node, a sensing output coupled to said load input;
• said sensing circuit providing negative feedback to said active load, and wherein
• an output signal at said a second transistor node swings substantially from 1.1 to 1.4 volts, when the device is energized from a voltage source of 1.4 volts and an input signal at said first transistor node swings substantially from 1.4 to 1.1.

An electrical device comprising:

• a logic circuit having at least one logic input node adapted to accept an external signal and forming a device input, at least one logic output node, and at least one logic bias node directly connected to a first current source;
• an active load transistor for each said logic output node each active load transistor having a first load node directly connected to a corresponding logic output node, a second load node directly connected to a power rail, and a third load node for receiving a load control signal;
• a bias transistor for each load transistor, each bias transistor having a first bias node directly connected to said corresponding logic output node, a second bias node directly connected to said power rail, and a third bias node directly connected both to a second constant current source and to said third load node for supplying said load control signal;
• wherein an output signal swing of the logic output node is substantially equal to an input signal swing of the external signal at the logic input node.

An electrical device comprising:

• a logic circuit having at least one logic input node adapted to accept an external signal and forming a device input, at least one logic output node, and at least one logic bias node connected to a first current source;
• an active load transistor for each said logic output node, each active load transistor having a first load node connected to a corresponding logic output node, a second load node connected to a power rail, and a third load node for receiving a load control signal;
• and
• a bias transistor for each load transistor, each bias transistor having a first bias node connected to said corresponding logic output node, a second bias node connected to said power rail, and a third bias node connected both to a second current source and to said third load node for supplying said load control signal, and wherein
• an output signal at said at least one logic output node swings substantially from 1.1 to 1.4 volts, when the device is energized from a voltage source of 1.4 volts and a signal at least one logic input node swings substantially from 1.4 to 1.1.