Programmable logic array integrated circuit devices with interleaved logic array blocks

A programmable logic array integrated circuit device comprising:

• a plurality of regions of programmable logic, each of which includes a plurality of modules of programmable logic, each module having a plurality of inputs and an output and being programmable to produce as said output any of a plurality of logic functions of the inputs of that module;
• a plurality of inter-region conductors adjacent to each of said regions, the inter-region conductors adjacent to each region including three subpluralities of said inter-region conductors, the conductors in a first of said subpluralities extending adjacent to a first relatively large number of said regions, the conductors in a second of said subpluralities extending adjacent to a second relatively small number of said regions, and the conductors in a third of said subpluralities extending adjacent to a third number of said regions which is even smaller than said second number;
• a plurality of local conductors associated with each of said regions;
• first programmable logic connectors for selectively connecting inter-region conductors adjacent to each region with local conductors associated with that region;
• second programmable logic connectors for selectively connecting local conductors associated with each region to the inputs of the modules of that region;
• and
• third programmable logic connectors for selectively connecting the outputs of the modules of each region to inter-region conductors adjacent to said region.

A programmable logic array integrated circuit device comprising:

• a plurality of regions of programmable logic disposed on said device in a two-dimensional array of intersecting rows and columns of said regions, each of said regions including a plurality of modules of programmable logic, each having a plurality of inputs adjacent a side of the region which includes that module and an output and being programmable to produce as said output any one of a plurality of logic functions of said inputs, all of said inputs of each of said modules being usable in parallel as logical inputs to the logic function performed by that module to produce said output of that module;
• a plurality of row conductors adjacent to each of said rows for conveying signals along said row;
• a plurality of column conductors adjacent to each of said columns for conveying signals along said column;
• a plurality of local conductors associated with each of said regions, the local conductors associated with each of said regions being disposed adjacent said side of that region;
• first programmable logic connectors for selectively connecting row conductors adjacent to each region with local conductors associated with that region;
• second programmable logic connectors for selectively connecting column conductors adjacent to each region with local conductors associated with that region;
• third programmable logic connectors for selectively connecting local conductors associated with each region to the inputs of the modules of that region;
• and
• fourth programmable logic connectors for selectively connecting the output of each module of each region to at least one conductor adjacent to that region, wherein a local conductor associated with each of said regions includes:
• a first segment to which said first and second programmable logic connectors are connected;
• a second segment to which said third and fourth programmable logic connectors are connected;
• and
• a fifth programmable logic connector for selectively connecting said first and second segments to one another.

A programmable logic array integrated circuit device comprising:

• a plurality of regions of programmable logic, each of said regions being programmable to produce a first output signal which is any of a plurality of logic functions of a plurality of region input signals applied to that region, each of said regions including a register for registering a signal applied to the register and producing a second output signal indicative of the signal registered by the register, and each of said regions further including a first programmable logic connector for selectively applying either said first output signal or a region input signal to the register;
• a plurality of first conductors extending adjacent to said regions for conveying signals between the regions;
• and
• a plurality of second conductors associated with each of said regions for (1) selectively conveying signals to the associated region for use as region input signals of the associated region, and (2) conveying output signals from the associated region, at least some of said second conductors being connectable to said first conductors, wherein each of said regions further includes second and third programmable logic connectors, both of which are uniquely associated with said register of said region and with no other register on said device, and each of which can apply a signal indicative of either of said first and second output signals to a respective one of said second conductors.

A programmable logic array integrated circuit device comprising:

• a plurality of regions of programmable logic disposed on said device in a two-dimensional array of intersecting rows and columns of said regions, each of said regions including a plurality of modules of programmable logic disposed in a linear array in that region, each module having a plurality of inputs and an output and being programmable to produce as said output any one of a plurality of logic functions of said inputs;
• a plurality of row conductors adjacent to each of said rows for conveying signals along said row;
• a plurality of column conductors adjacent to each of said columns for conveying signals along said column;
• a plurality of local conductors associated with each of said regions and extending along the linear array of modules in that region;
• first programmable logic connectors for selectively connecting row conductors adjacent to each region with local conductors associated with that region;
• second programmable logic connectors for selectively connecting column conductors adjacent to each region with local conductors associated with that region;
• third programmable logic connectors for selectively connecting local conductors associated with each region to the inputs of the modules of that region;
• and
• fourth programmable logic connectors for selectively connecting the output of each module of each region to at least one conductor adjacent to that region, wherein a local conductor associated with each of said regions includes:
• a first segment to which at least one of said first and at least one of said second programmable logic connectors are connected;
• a second segment to which at least one of said third and at least one of said fourth programmable logic connectors are connected;
• and
• a fifth programmable logic connector for selectively connecting said first and second segments to one another.