Fabrication method for reduced-dimension FET devices

In an integrated circuit fabrication method for fabricating MOSFETs on a semiconductor substrate, wherein adjacent FETs are separated from one another by isolation elements and each fabricated FET comprises (1) a semiconductor gate built up over (2) the surface of an appropriately-doped single crystalline semiconductor well, (3) first and second sidewall spacers situated, respectively, on either side of said semiconductor gate, (4) a relatively deep appropriately-doped single crystalline semiconductor source extending longitudinally from a first isolation element to a part adjacent to said first sidewall spacer, (5) a relatively deep appropriately-doped semiconductor drain extending longitudinally from a second isolation element to a part adjacent to said second sidewall spacer, (6) a first ultra-shallow semiconductor extension situated under said first sidewall spacer for connecting said source to a gate edge proximate thereto, and (7) a second ultra-shallow semiconductor extension situated under said second sidewall spacer for connecting said drain to a gate edge proximate thereto;

• wherein said method comprises the following steps for fabricating each of said first and second ultra-shallow, doped semiconductor extensions subsequent to the fabrication of said well and said semiconductor gate and prior to the fabrication of said first and second sidewall spacers:
• (a) ion implanting atoms of an appropriate element in each of first and second surface layers of said single crystalline semiconductor well that extend longitudinally from a gate edge of said semiconductor gate to an isolation element at a designed concentration per unit area and at an appropriate energy level to amorphize said first and second layers to a certain depth which is less than 100 nm deep;
• (b) depositing an amount of doping material to dope said extensions as a film in solid form on said first and second amorphized surface layers by decomposing an appropriate dopant compound in gaseous form with radiation to achieve a designed impurity level in said first and second amorphized surface layers;
• (c) applying a first pulse of a number of successive pulses of radiant energy from a pulsed laser to each of said of first and second amorphized surface layers to heat a first area for a duration of said first of said successive pulses, and thereafter serially applying other of said successive pulses of radiant energy from said pulsed laser to other areas of said first and second amorphized surface layers with each successive area overlapping the previous irradiated area of said first or second amorphized surface layer to heat each of said other areas for the duration of a single one of said successive pulses, the radiation energy of each separate one of said successive pulses being sufficient to heat said first or second amorphized surface layer in said area irradiated thereby to the melting temperature of said first or second amorphized surface layer and insufficient to heat said underlying crystalline semiconductor to the melting temperature of said underlying crystalline semiconductor;
• and
• (d) providing a time interval between the application of each successive pulse sufficient to permit the melted area of said first or second amorphized surface layers to recrystallize and cool to an initial temperature prior to the application of a successive pulse to said first or second amorphized surface layer.