Continuous byte-stream encoder/decoder using frequency increase and cyclic redundancy check
Assignee3Com Corporation
InventorsMiles Benson, Myles Kimmitt, Dan Ater
Life of this patent
Estimating the term…
Loading patent…
Assignee3Com Corporation
InventorsMiles Benson, Myles Kimmitt, Dan Ater
Estimating the term…
A continuous byte stream encoder/decoder process where a continuous stream of ATM data cells is received with a plurality of words, where each word has a plurality of bits in parallel. The ATM data cell is analyzed and new control words are created to convey information such as Start-of-Cell, parity and synchronization signals for the serializer and deserializer chip set. These control words are combined with the data words of the ATM data cell to form a combined word stream. This word stream having a higher word transfer rate than the original ATM data cell. This combined word stream is fed to a known 8B/10B encoder which further modifies the data for proper transmission over an AC coupled serial path. Data from the 8B/10B decoder is then serialized through known serialization/deserialization chip sets passed over the serial path and then deserialized back into an recombined word stream. This word stream is decoded both with a 8B/10B decoder and with a frequency decreasing decoder to restore the data to its original data cell format.
A continuous byte stream encoder/decoder process in an ATM (Asynchronous Transfer Mode) network, the process comprising:
Dependencies are inferred from the claim text.