Operational amplification circuit capable of driving a high load

An operational amplification circuit comprising:

• a first differential amplification circuit including a first MOS transistor of a first conductivity type having a gate connected to a first input terminal, and a second MOS transistor of the first conductivity type having a gate connected to a second input terminal and generating a first signal having a voltage level which reflects a voltage difference between the first input terminal and the second input terminal;
• a second differential amplification circuit including a third MOS transistor of the first conductivity type having a gate connected to the first input terminal, and a fourth MOS transistor of the first conductivity type having a gate connected to the second input terminal and generating a second signal having a voltage level which reflects a voltage difference between the second input terminal and the first input terminal;
• a level shift circuit including a fifth MOS transistor of a second conductivity type having a gate receiving the first signal, and a sixth MOS transistor of the first conductivity type, said level shift circuit generating a third signal having a level that is shifted from the voltage of the first signal;
• a current source circuit supplying a predetermined current to the sixth MOS transistor;
• and
• an output circuit including a seventh MOS transistor of the first conductivity type having a gate receiving the third signal, and an eighth MOS transistor of the second conductivity type having a gate receiving the second signal.

An operational amplification circuit comprising;

• a first differential amplification circuit including a first MOS transistor of a first conductivity type having a gate connected to a first input terminal, and a second MOS transistor of the first conductivity type having a gate connected to a second input terminal, the first differential amplification circuit generating a first signal having an amplified voltage in accordance with a voltage difference between the first input terminal and the second input terminal;
• a second differential amplification circuit including a third MOS transistor of a second conductivity type having a gate connected to the first input terminal, and a fourth MOS transistor of the second conductivity type having a gate connected to the second input terminal, the second differential amplification circuit generating a second signal having an amplified voltage in accordance with the voltage difference between the first input terminal and the second input terminal;
• a first level shift circuit including a fifth MOS transistor of the second conductivity type having a gate receiving the first signal, and a sixth MOS transistor of the first conductivity type, said first level shift circuit generating a third signal having a level that is shifted from the voltage of the first signal;
• a second level shift circuit including a seventh MOS transistor of the first conductivity type having a gate receiving the second signal, and an eighth MOS transistor of the second conductivity type, said second level shift circuit generating a fourth signal having a level that is shifted from the voltage of the second signal;
• a first current source circuit supplying a first predetermined current to the sixth MOS transistor;
• a second current source circuit supplying a second predetermined current to the eighth MOS transistor;
• and
• an output circuit including a ninth MOS transistor of the first conductivity type having a gate receiving the third signal, and a tenth MOS transistor of the second conductivity type having a gate receiving the fourth signal, said output circuit generating an output signal in response to the third and fourth signals.