Microprocessor adapted for executing both a non-compressed fixed length instruction set and a compressed variable length instruction set

A method for executing programs created by a programmer in a variable-length instruction set, comprising:

• fetching instructions which are members of the variable-length instruction set, wherein said variable length instruction set consists of a first plurality of instructions having a first fixed length and a second plurality of instructions having a second fixed length different from said first length, wherein each of said first plurality of instructions and said second plurality of instructions comprise an opcode field and one or more operands fields, and wherein said first plurality of instructions are identified by a first encoding of said opcode field, and wherein said second plurality of instructions are identified by remaining encodings of said opcode field, and wherein each of said first plurality of instructions further includes a second opcode field;
• decompressing said instructions in an instruction decompressor, thereby forming corresponding corresponding instructions from a fixed length instruction set, wherein said decompressing comprises:
• (i) decompressing said second opcode field of said received instruction into an opcode field of said corresponding instruction upon detection of said first encoding, and (ii) decompressing said opcode field of said received instruction into said opcode field of said corresponding instruction upon detection of one of said remaining encodings;
• and
• executing said correspond instructions in a processor core.

An apparatus for executing programs created by a programmer in a variable-length instruction set, comprising:

• a fetching means for fetching instructions which are members of the variable-length compressed instruction set, wherein said variable length compressed instruction set consists of a first plurality of instructions having a first fixed length and a second plurality of instructions having a second fixed length different from said first length, wherein each of said first plurality of instructions and said second plurality of instructions comprise an opcode field and one or more operand fields, and wherein said first plurality of instructions are identified by a first encoding of said opcode field, and wherein said second plurality of instructions are identified by remaining encodings of said opcode field, and wherein each of said first plurality of instructions further includes a second opcode field;
• a decompressing means for decompressing said instructions, thereby forming corresponding instructions, wherein said decompressing means is configured to decompress said second opcode field of said received instruction into an opcode field of said corresponding instruction upon detection of said first encoding, and wherein said decompressing means is configured to decompress said opcode field of said received instruction into said opcode field of said corresponding instruction upon detection of one of said remaining encodings;
• and
• an executing means for executing said corresponding instructions.