Modulo address generating circuit and method with reduced area and delay using low speed adders

A modulo address generator comprising:

• a first adder configured to receive a current address value and an address increment value and add the current address value and the address increment value to generate an incremented address value;
• an inverter configured to receive a maximum address value of a data region and generate a complemented maximum address value;
• a second adder configured to receive the complemented maximum address value and a minimum address value of the data region and add the complemented maximum address value and the minimum address value to generate a circular correction value;
• an adder/subtracter configured to receive the incremented address value, the circular correction value and a sign bit of the address increment value, wherein the adder/subtracter is further configured to add the incremented address value and the circular correction value responsive to a positive value of the sign bit and subtract the circular correction value from the incremented address value responsive to a negative value of the sign bit in order to generate a corrected address value;
• a comparator configured to receive the incremented address value, determine whether the incremented address value is within an address range defined by the maximum and minimum addresses, and generate a selection signal having a first logic value when the incremented address value is within the address range and a second logic value when the incremented address value is outside the address range;
• and
• a multiplexor configured to receive the incremented address value, the corrected address value and the selection signal, wherein the multiplexor is further configured to select the incremented address value for output as a next address responsive to the first logic value of the selection signal and select the corrected address value for output as the next address responsive to the second logic value of the selection signal.