Accelerated Graphics Port two level Gart cache having distributed first level caches

A computer system having a core logic chipset which connects a computer processor and memory to an accelerated graphics port (AGP) processor, said system comprising:

• a system processor executing software instructions and generating graphics data;
• a system memory having an addressable memory space comprising a plurality of bytes of storage, wherein each of the plurality of bytes of storage has a unique address;
• the software instructions and the graphics data being stored in some of the plurality of bytes of storage of said system memory, wherein the graphics data is stored in a plurality of pages of graphics data, each of the plurality of pages of graphics data comprising a number of the plurality of bytes of storage;
• an accelerated graphics port (AGP) processor generating video display data from the graphics data and adapted for connection to a video display to display the video display data;
• a core logic chipset having a common second-level cache memory;
• said core logic chipset having a first interface logic for connecting said system processor to said system memory;
• said first interface logic having a first first-level cache memory, said first first-level cache memory connected to said common second-level cache memory;
• said core logic chipset having a second interface logic for connecting said system processor and said system memory to said AGP processor;
• said second interface logic having a second first-level cache memory, said second first-level cache memory connected to said common second-level cache memory;
• a graphics address remapping table (GART table) having a plurality of entries, each of the plurality of GART table entries comprising an address pointer to a corresponding system memory address of each of the plurality of pages of graphics data, the plurality of GART table entries being stored in some other of the plurality of bytes of storage of said system memory and each of the plurality of GART table entries being associated with a block of graphics device addresses;
• said AGP processor requests a graphics data transaction by asserting a graphics device address to said second interface logic;
• and
• said second interface logic determines if a required one of the plurality of GART table entries is stored in said second first-level cache memory, wherein:
• if the required one of the plurality of GART table entries is stored in said second first-level cache memory then said second interface logic uses the required one of the plurality of GART table entries to translate the graphics device address of the requested graphics data transaction to a corresponding address of a one of the plurality of pages of graphics data stored in said system memory;
• if the required one of the plurality of GART table entries is not stored in said second first-level cache memory, then said core logic chipset determines if the required one of the plurality of GART table entries is stored in said common second-level cache memory;
• if the required one of the plurality of GART table entries is stored in said common second-level cache memory, then said core logic chipset stores the required one in said second first-level cache memory, and said second interface logic uses the required one of the plurality of GART table entries to translate the graphics device address of the requested graphics data transaction to the corresponding address of the one of the plurality of pages of graphics data stored in said system memory;
• and
• if the required one of the plurality of GART table entries is not stored in said common second-level cache memory, then said core logic chipset accesses said system memory to obtain the required one of the plurality of GART table entries from said GART table, said core logic chipset stores the required one of the plurality of GART table entries from said GART table in said common second-level cache memory and said second first-level cache memory, and said second interface logic uses the required one of the plurality of GART table entries to translate the graphics device address of the requested graphics data transaction to the corresponding address of the one of the plurality of pages of graphics data stored in said system memory.