CMOS integrated circuit regulator for reducing power supply noise

A CMOS integrated circuit regulator for reducing noise in a mixed-mode circuit including CMOS logic, the CMOS logic including at least one gate having at least one logic state, the regulator comprising:

• a pair of power supply rails coupled to the CMOS logic;
• a source follower circuit coupled to the supply rails;
• a current source coupled to each supply rail;
• charge means coupled to the supply rails and electrically connected in parallel with the CMOS logic, to ensure that current is provided to CMOS logic during a transition in the logic state.

A method, for use with a CMOS integrated circuit regulator, for reducing noise in a mixed-mode circuit including CMOS logic, the CMOS logic including at least one gate having at least one logic state, the method comprising:

• coupling a pair of power supply rails to the CMOS logic and coupling a current source to at least one of the power supply rails;
• clamping the level of the power supply rails when the CMOS logic is in a quiescent state;
• charging a capacitor coupled to the supply rails electrically in parallel with the CMOS logic when the CMOS logic is in a quiescent state;
• and
• supplying current to the CMOS logic from at least one of the current source and the capacitor during a transition in the logic state to minimize generation of noise resulting from the transition.