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US 5,905,292 AGranted
Semiconductor device in which an increase in threshold voltage, resulting from back-gate bias effect is mitigated, and method of manufacturing the same
AssigneeKabushiki Kaisha Toshiba
InventorsSouichi Sugiura, Masaru Koyanagi
Life of this patent
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Abstract
Disclosed herein is a semiconductor device comprising a semiconductor substrate, a well region provided in the surface of the substrate, a plurality of MOSFETs provided in the well region. The well region has parts having a low surface impurity concentration. Some of the MOSFETs have their channel regions provided in those parts of the well region which have the low surface impurity concentration. The other MOSFETs have their channel regions provided in other parts of the well region.
Claims24
A semiconductor device comprising:
- a semiconductor substrate;
- a well region of a first conductivity type formed in said semiconductor substrate, said well region including a first surface portion of the first conductivity type having a first surface impurity concentration and a second surface portion of the first conductivity type having a second surface impurity concentration, said first surface impurity concentration lower than the second surface impurity concentration;
- at least one insulated-gate field effect transistor including a channel region, a source region of a second conductivity type and a drain region of the second conductivity type, said channel region formed in said first surface portion of said well region, said source region and said drain region each formed in said second surface portion of said well region.
A semiconductor device comprising:
- a semiconductor substrate;
- a well region of a first conductivity type formed in said semiconductor substrate, said well region including a first surface portion of the first conductivity type and a second surface portion of the first conductivity type, a junction between said well region and said semiconductor substrate being at a first depth below said first surface portion, the junction between said well region and said semiconductor substrate being at a second depth below said second surface portion, said first depth being shallower than said second depth;
- and
- at least one insulated-gate field effect transistor including a channel region, a source region of a second conductivity type and a drain region of the second conductivity type, said channel region formed in said first surface portion of said well region, said source region and said drain region each formed in said second surface portion of said well region.
1 more element
A semiconductor device comprising:
- a semiconductor substrate;
- a well region of a first conductivity type formed in said semiconductor substrate, said well region including a first surface portion of the first conductivity type having a first surface impurity concentration and a second surface portion of the first conductivity type having a second surface impurity concentration, said first surface impurity concentration being less than the second surface impurity concentration, a junction between said well region and said semiconductor substrate being at a first depth below said first surface portion, the junction between said well region and said semiconductor substrate being at a second depth below said second surface portion, said first depth being shallower than said second depth;
- and
- at least one insulated-gate field effect transistor including a channel region, a source region of a second conductivity type and a drain region of the second conductivity type, said channel region formed in said first surface portion of said well region, said source region and said drain region each formed in said second surface portion of said well region.
1 more element
Dependencies are inferred from the claim text.