Dynamic branch prediction for branch instructions with multiple targets

A method for predicting the target address of an instruction bundle containing multiple single-target branch instructions, the method comprising the steps of:

• storing information indicating a branch activity history of each single-target branch instruction of the instruction bundle;
• using the information indicating the branch activity history of each single-target branch instruction to predict an outcome of a next execution of each single-target branch instruction;
• storing a predicate prediction containing the predictions of the outcome of the next execution of each single-target branch instruction in a table entry associated with the instruction bundle;
• and
• predicting an outcome of the instruction bundle based on the predicate prediction.

A branch prediction table in a microprocessor having an instruction cache containing an instruction bundle consisting of two or more branch instructions, the branch prediction table comprising:

• a tag entry associated with the instruction bundle;
• prediction history information for each branch instruction of the instruction bundle stored in the table entry corresponding to the tag associated with the instruction bundle;
• and
• a predicate prediction indicating a prediction of whether a branch instruction will be taken, and if a branch instruction will be taken, indicating a prediction of which branch in the branch bundle will be taken.

A branch prediction table in a microprocessor having an instruction cache containing a multiple-target branch instruction, where the multiple-target branch instruction has at least two associated target addresses which are not a fall-through address, the branch prediction table comprising:

• a tag entry associated with the multiple-target branch instruction;
• prediction history information for the multiple-target branch instruction stored in a table entry corresponding to the tag associated with the multiple-target branch instruction;
• and
• a predicate prediction indicating a prediction of whether a branch will be taken, and if a branch instruction will be taken, indicating a prediction of which target addresses of the multiple target addresses will be taken.

A processor comprising:

• an instruction cache containing an instruction bundle consisting of two or more branch instructions;
• a branch prediction table couple to the instruction cache for indicating a prediction of a target address for the instruction bundle, the branch prediction table comprising:
• a tag entry associated with the instruction bundle;
• prediction history information for each branch instruction of the instruction bundle stored in the table entry corresponding to the tag associated with the instruction bundle;
• and
• a predicate prediction indicating a prediction of whether a branch instruction will be taken, and if a branch instruction will be taken, indicating a prediction of which branch in the branch bundle will be taken.

A processor comprising:

• an instruction cache containing a multiple-target branch instruction, where the multiple-target branch instruction has at least two associated target addresses which are not a fall-through address;
• a branch prediction table coupled to the instruction cache for indicating a prediction of a target address for the multiple-target branch instruction, the branch prediction table comprising:
• a tag entry associated with the multiple-target branch instruction;
• prediction history information for the multiple-target branch instruction stored in a table entry corresponding to the tag associated with the multiple-target branch instruction;
• and
• a predicate prediction indicating a prediction of whether a branch will be taken, and if a branch instruction will be taken, indicating a prediction of which target addresses of the multiple target addresses will be taken.