Semiconductor memory device and various systems mounting them

An IC card comprising an IC chip having a semiconductor memory,

• wherein said semiconductor memory includes a plurality of memory cells each having a transistor having a source terminal and a drain terminal and a ferroelectric capacitor having a first terminal connected to said source terminal and a second terminal connected to said drain terminal;
• a predetermined number of said memory cells are connected in series to constitute a memory cell block;
• and
• a plurality of memory cell blocks are arranged to constitute a cell array.

A digital image input system comprising:

• an image input device for inputting image data;
• a data compression device for compressing the input image data;
• a semiconductor memory for storing the compressed image data;
• an output device for outputting the compressed image data;
• and
• a display device for displaying one of the input image data ani the compressed image data;
• wherein said semiconductor memory includes a plurality of memory cells each having a transistor having a source terminal and a drain terminal and a ferroelectric capacitor having a first terminal connected to said source terminal and a second terminal connected to said drain terminal;
• a predetermined number of said memory cells are connected in series to constitute a memory cell block;
• and
• a plurality of memory cell blocks are arranged to constitute a cell array.

A memory system comprising:

• a semiconductor memory for storing data;
• and
• an input/output device connected to said semiconductor memory to send/receive data to/from an external device;
• wherein said semiconductor memory includes a plurality of memory cells each having a transistor having a source terminal and a drain terminal and a ferroelectric capacitor having a first terminal connected to said source terminal and a second terminal connected to said drain terminal;
• a predetermined number of said memory cells are connected in series to constitute a memory cell block;
• and
• a plurality of memory cell blocks are arranged to constitute a cell array.

A system LSI chip comprising:

• a core section for performing various processing operations;
• and a semiconductor memory for storing data;
• wherein said semiconductor memory includes a plurality of memory cells each having a transistor having a source terminal and a drain terminal and ferroelectric capacitor having a first terminal connected to said source terminal and a second terminal connected to said drain terminal;
• a predetermined number of said memory cells are connected in series to constitute a memory cell block;
• and
• a plurality of memory cell blocks are arranged to constitute a cell array.

A mobile computer system comprising:

• a microprocessor;
• an input device connected to said microprocessor to input data;
• a radio wave sending/receiving device connected to said microprocessor to send/receive data to/from an external device;
• an antenna connected to said sending/receiving device;
• a display device connected to said microprocessor to display necessary information;
• and
• a semiconductor memory device connected to said microprocessor to store data;
• wherein said semiconductor memory includes a plurality of memory cells each having a transistor having a source terminal and a drain terminal and a ferroelectric capacitor having a first terminal connected to said source terminal and a second terminal connected to said drain terminal;
• a predetermined number of said memory cells are connected in series to constitute a memory cell block;
• and
• a plurality of memory cell blocks are arranged to constitute a cell array.

A method of driving a semicorductor memory which comprises a plurality of memory cells each having a transistor having a source terminal and a drain terminal and a ferroelectric capacitor having a first terminal connected to said source terminal and a second terminal connected to said drain terminal, a predetermined number of memory cells being connected in series to constitute a memory cell block, and has a random access function, comprising the steps of:

• the first step of turning on transistors of said plurality of memory cells in said memory cell block;
• the second step of setting a transistor of any one of said plurality of memory cells in said memory cell block in an OFF state to select the memory cell, and applying, to said selected memory cell, a voltage higher than a first minimum coercive voltage of coercive voltages of said ferroelectric capacitors, thereby reading out information stored in said ferroelectric capacitor having the first coercive voltage;
• the third step of writing a voltage higher than the first coercive voltage in said selected memory cell;
• the fourth step of applying a voltage higher than a second coercive voltage higher than the first coercive voltage to said selected memory cell, thereby reading out information stored in said ferroelectric capacitor having the second coercive voltage;
• and
• the fifth step of writing a voltage higher than the second coercive voltage in said selected memory cell.