Conductive bumps on die for flip chip application

An under bump metallization formed in at least one via defined in at least one passivation layer over a semiconductor substrate, wherein edges of said under bump metallization are substantially flush with an exposed surface of said passivation layer to define a discrete metal-covered via for connection with external electrical components, fabricated by a method comprising:

• providing said semiconductor substrate including integrated circuitry, and said at least one passivation layer having a thickness and disposed over said semiconductor substrate;
• providing access to said integrated circuitry for external contact by forming said at least one via extending through said at least one passivation layer;
• forming a substantially conformal metal layer of a thickness substantially less than the passivation layer thickness over said at least one passivation layer with a portion of said metal layer extending into said at least one via to make electrical contact with said integrated circuitry;
• and
• removing said metal layer only above said at least one passivation layer by abrasive contact.

An under bump metallization formed in at least one via defined in at least one passivation layer over a semiconductor substrate, wherein edges of said under bump metallization are substantially flush with an exposed surface of said passivation layer to define a discrete metal-covered via for connection with external electrical components, fabricated by a method comprising:

• providing a semiconductor substrate including integrated circuitry, and said at least one passivation layer having a thickness and disposed over said semiconductor substrate;
• providing access to said integrated circuitry for external contact by forming at least one via extending through said at least one passivation layer;
• forming a substantially conformal metal layer of a thickness substantially less than the passivation layer thickness over said at least one passivation layer with a portion of said metal layer extending into said at least one via to make electrical contact with said integrated circuitry;
• applying an etchant-resistive material over said metal layer and into said at least one via so as to substantially fill said at least one via;
• removing a portion of said etchant-resistive material to expose said metal layer only above said at least one passivation layer;
• removing said metal layer over said at least one passivation layer except for the portion extending into said at least one via by applying an etchant to said exposed metal layer above said at least one passivation layer while protecting said metal layer portion extending into said at least one via with said etchant-resistive material;
• and
• removing said etchant-resistive material within said at least one via.