System and method for performing software patches in embedded systems

A embedded system configured to receive a software patch, comprising:

• an embedded system device comprising:
• a processor including a breakpoint register and a program counter, each containing a value;
• a non-alterable memory coupled to said processor, wherein said nonalterable memory includes instructions executable by said processor;
• and
• an alterable memory coupled to said processor configured to store a patch, wherein said patch comprises patch instructions executable by said processor;
• and
• an external memory operably coupled to said device including said patch;
• wherein said processor is configured to load said patch from said external memory to said alterable memory and to execute said patch, wherein said patch is encrypted prior to being loaded into said alterable memory, and wherein said device is configured to decrypt said patch when loading said patch into said alterable memory.

A method for executing a patch in an embedded system device comprising a processor including a breakpoint register and a program counter, each containing a value, a non-alterable memory coupled to said processor, wherein said non-alterable memory includes instructions executable by said processor, and an alterable memory coupled to said processor configured to store a patch, wherein a portion of said patch comprises patch instructions executable by said processor, the method comprising:

• initializing said program counter to a value;
• loading said breakpoint register with a breakpoint address;
• determining a presence of said patch after said initializing said program counter value and before said loading said breakpoint register;
• loading said patch into said alterable memory before said loading said breakpoint register if said patch is present;
• encrypting said patch prior to said initializing said program counter to a value;
• decrypting said encrypted patch during said loading said patch;
• fetching an instruction from said non-alterable memory at an address equal to said program counter value;
• incrementing said program counter in response to said fetching;
• executing said instruction;
• performing said fetching, said incrementing and said executing until said program counter value equals said breakpoint register value;
• deviating from said fetching, said incrementing and said executing when said program counter value equals said breakpoint address;
• executing a plurality of patch instructions of a patch included in said alterable memory in response to said deviating.

A method for executing a series of patches in an embedded system device comprising a processor including a breakpoint register and a program counter, each containing a value, a non-alterable memory coupled to said processor, wherein said non-alterable memory includes firmware instructions executable by said processor, and an alterable memory coupled to said processor configured to store said series of patches, wherein a portion of each of said series of patches comprises patch instructions executable by said processor, the method comprising:

• executing said firmware instructions;
• loading a first of said series of patches into said alterable memory;
• loading said breakpoint register with a first breakpoint address after said loading said first of said series of patches;
• deviating from said executing said firmware instruction when said program counter value equals said first breakpoint address;
• executing said first of said series of patches in response to said deviating from said executing said firmware instructions;
• loading a second of said series of patches into said alterable memory;
• loading said breakpoint register with a second breakpoint address after said loading said second of said series of patches;
• deviating from said executing said first of said series of patches when said program counter value equals said second breakpoint address;
• executing said second of said series of patches in response to said deviating from said executing said first of said series of patches.

A method for executing a series of patches in an embedded system device comprising a processor including a breakpoint register and a program counter, each containing a value, a non-alterable memory coupled to said processor, wherein said non-alterable memory includes firmware instructions executable by said processor, and an alterable memory coupled to said processor configured to store said series of patches, wherein a portion of each of said series of patches comprises patch instructions executable by said processor, the method comprising:

• loading a first of said series of patches into said alterable memory;
• loading a second of said series of patches into said alterable memory;
• loading said breakpoint register with a first breakpoint address after said loading said first and second of said series of patches;
• executing said firmware instructions;
• deviating from said executing said firmware instruction when said program counter value equals said first breakpoint address;
• executing said first of said series of patches in response to said deviating from said executing said firmware instructions;
• loading said breakpoint register with a second breakpoint address after said loading said second of said series of patches;
• deviating from said executing said first of said series of patches when said program counter value equals said second breakpoint address;
• executing said second of said series of patches in response to said deviating from said executing said first of said series of patches.

A method for replacing a patch in an embedded system device comprising a processor including a breakpoint register and a program counter, each containing a value, a non-alterable memory coupled to said processor, wherein said non-alterable memory includes firmware instructions executable by said processor, and an alterable memory coupled to said processor configured to store said series of patches, wherein a portion of each of said series of patches comprises patch instructions executable by said processor, the method comprising:

• loading a first patch into said alterable memory;
• loading said breakpoint register with a first breakpoint address after said loading said first patch;
• executing said firmware instructions;
• deviating from said executing said firmware instruction when said program counter value equals said first breakpoint address;
• executing said first patch in response to said deviating from said executing said firmware instructions;
• loading a second patch into said alterable memory;
• loading said breakpoint register with a second breakpoint address after said loading said second patch;
• deviating from said executing said first patch when said program counter value equals said second breakpoint address;
• executing said second patch in response to said deviating from said executing said first patch.