Dynamic random access memory having decoding circuitry for partial memory blocks

A semiconductor memory device, comprising an array of rows and columns of memory cells each disposed at an intersection between a digit line and a word line, wherein said array of rows and columns of memory cells is subdivided into a plurality of substantially equivalent partial arrays of rows and columns of memory cells, said plurality of partial arrays physically arranged in a plurality of adjacent pairs of partial arrays such that each pair of partial arrays defines a first type of elongate intermediate area between the partial arrays of each pair of partial arrays, and said partial arrays being further subdivided into a plurality of sub-arrays, said sub-arrays physically arranged in a plurality of adjacent pairs such that each pair of sub-arrays defines a second type of elongate intermediate area between the sub-arrays of each pair of sub-arrays, said memory device further comprising:

• for each of said plurality of adjacent pairs of partial arrays, row address predecoding circuitry, disposed in said first type of intermediate area, responsive to row address signals supplied to said device to generate a plurality of predecoded row address signals;
• and
• a plurality of row decoder driver circuits, each disposed in one of said second type of elongate intermediate areas and each coupled to said row address predecoding circuitry, said row decoder driver circuits responsive to said predecoded row address signals to generate local row address signals;
• a plurality of local row address decoding circuits, distributed throughout said sub arrays and each electrically coupled to one of said row row decoder driver circuits to receive said local row address signals, said local row decoding circuits selectively responsive to said local row address signals to apply at least one word line driving signal to its associated subarray during a memory access cycle.