Stabilization circuits and techniques for storage and retrieval of single or multiple digital bits per memory cell

An integrated circuit memory circuit system comprising:

• an array of memory cells, each memory cell capable of storing one of 2.sup.N discrete amounts of electric charge corresponding to N digital information bits, each amount in a preselected range;
• a programming circuit coupled to said memory cell array, said programming circuit supplying signals to said memory cell array to move electric charge to and from said memory cells so that charge stored in said memory cells corresponds to said digital information bits;
• a reference voltage circuit capable of generating a first and second set of reference voltages, each set of reference voltages corresponding to a preselected range of electric charge stored in one of said memory cells corresponding to digital information bits, said second set of reference voltages corresponding to a narrower range than said first set of reference voltages;
• comparators coupled to said memory cell array and said reference voltage circuit;
• and
• control circuitry coupled to said memory cell array, said reference voltage circuit, said comparators and said programming circuit, said control circuitry connecting a plurality of memory cells in said memory cell array to said programming circuit and said comparators to program charge in each memory cell of said plurality of memory cells, said charge programmed in a preselected range corresponding to said first set of reference voltages, said control circuitry subsequently connecting said comparators to said memory cell array and said reference voltage circuit to sense said charge outside of a preselected range corresponding to said second set of reference voltages in each memory cell of said plurality, and engaging said programming circuit to restore said charge in said preselected range corresponding to said second set of reference voltages in said memory cell.