Fabrication of semiconductor structure having two levels of buried regions

A method of fabricating an integrated semiconductor structure from a semiconductive substrate which comprises a major region of a first conductivity type, the method comprising the steps of:

• introducing first semiconductor dopant of a second conductivity type opposite to the first conductivity type into the major region to create a vertical isolation region of the second conductivity type;
• introducing second semiconductor dopant of the second conductivity type into the major region to define a first lateral isolation region of the second conductivity type continuous with the vertical isolation region, the second dopant having a greater diffusivity than the first dopant;
• and
• forming (a) a semiconductive layer over the major region such that part of each of the first and second dopants diffuses into the semiconductor layer to expand the vertical and first lateral isolation regions into the semiconductive layer and (b) a transistor from material of the semiconductive layer overlying the vertical isolation region, the second dopant diffusing further into the semiconductive layer than the first dopant whereby the first lateral isolation region expands into the semiconductive layer to provide at least partial lateral junction isolation for the transistor while the vertical isolation region expands into the semiconductive layer to at least partially isolate the transistor from first conductivity type material of the major region.

A method of fabricating an integrated semiconductor structure from a semiconductive substrate which comprises a major region of a first conductivity type, the method comprising the steps of:

• introducing semiconductor dopant of a second conductivity type opposite to the first conductivity type into the major region to create a vertical isolation region of the second conductivity type;
• forming a lower semiconductive layer over the major region so that the vertical isolation region updiffuses partway through the lower layer and so that first semiconductor dopant of the first conductivity type enters the lower layer to form a buffer region of the first conductivity type over the vertical isolation region;
• introducing second semiconductor dopant of the first conductivity type into the lower layer to form over the buffer region a first collector zone of the first conductivity type for a first vertical bipolar transistor;
• forming an upper semiconductive layer over the lower layer;
• providing a second collector zone of the first conductivity type in the upper layer such that the second collector zone meets the first collector zone;
• and
• providing the first bipolar transistor with a base zone of the second conductivity type and an emitter zone of the first conductivity type.

A method comprising the steps of:

• forming a semiconductor structure that comprises (a) a monocrystalline semiconductive substrate, (b) a lower monocrystalline semiconductive layer provided over the substrate such that the lower semiconductive layer adjoins the substrate along a lower semiconductor interface, and (c) an upper monocrystalline semiconductive layer provided over the lower semiconductive layer such that the upper semiconductive layer adjoins the lower semiconductive layer along an upper semiconductor interface;
• introducing (a) first and second semiconductor dopants of opposite conductivity types into semiconductive material of the structure to respectively form first and second lower buried regions of opposite conductivity types along the lower semiconductor interface and (b) third and fourth semiconductor dopants of opposite conductivity types into semiconductive material of the structure to respectively form first and second upper buried regions of opposite conductivity types along the upper semiconductor interface;
• and
• introducing at least one semiconductor dopant selectively into the upper semiconductive layer to define a plurality of P-type device regions and a plurality of N-type device regions such that one of the device regions of each conductivity type laterally meets one of the device regions of the other conductivity type and vertically extends into the upper semiconductive layer to a depth sufficient to meet one of the upper buried regions.

A method comprising the steps of:

• introducing first and second semiconductor dopants of opposite conductivity types selectively into a monocrystalline semiconductive substrate;
• providing a lower monocrystalline semiconductive layer over the substrate such that (a) the lower semiconductive layer adjoins the substrate along a lower semiconductor interface and (b) the first and second dopants respectively form first and second lower buried regions of opposite conductivity types along the lower semiconductor interface;
• introducing third semiconductor dopant of a selected conductivity type selectively into the lower semiconductive layer;
• providing an upper monocrystalline semiconductive layer over the lower semiconductive layer such that (a) the upper semiconductive layer adjoins the lower semiconductive layer along the upper semiconductor interface and (b) the third dopant forms an upper buried region of the selected conductivity type along the upper semiconductor interface;
• and
• introducing semiconductor dopants of opposite conductivity types selectively into the upper semiconductive layer to define a plurality of P-type device regions and a plurality of N-type device regions such that one of the device regions of each conductivity type laterally meets one of the device regions of the other conductivity type, each device region vertically extending largely through the upper semiconductive layer, the dopants being introduced into the substrate and the upper and lower semiconductive layers at such locations that at least one of each of the P-type and N-type device regions is vertically electrically isolated from the substrate, one of the so-isolated device regions, including any directly underlying semiconductive material of the same conductivity type as that device region, being surrounded within the upper and lower semiconductive layers and the substrate by semiconductive material which is of opposite conductivity type to that so-isolated device region and which comprises (a) another of the device regions, (b) the upper buried region, and (c) one of the lower buried regions connected through the lower semiconductive layer to the upper buried region.

A method comprising the steps of:

• introducing first and second semiconductor dopants of opposite conductivity types selectively into a monocrystalline semiconductive substrate;
• providing a lower monocrystalline semiconductive layer over the substrate such that (a) the lower semiconductive layer adjoins the substrate along a lower semiconductor interface and (b) the first and second dopants respectively form first and second lower buried regions of opposite conductivity types along the lower semiconductor interface;
• introducing third semiconductor dopant of a selected conductivity type selectively into the lower semiconductive layer;
• providing an upper monocrystalline semiconductive layer over the lower semiconductive layer such that (a) the upper semiconductive layer adjoins the lower semiconductive layer along the upper semiconductor interface and (b) the third dopant forms an upper buried region of the selected conductivity type along the upper semiconductor interface;
• and
• introducing semiconductor dopants of opposite conductivity types selectively into the upper semiconductive layer to define a plurality of P-type device regions and a plurality of N-type device regions, each device region extending largely through the upper semiconductive layer, the dopants being introduced into the substrate and the upper and lower semiconductive layers at such locations that at least one of each of the P-type and N-type device regions is vertically electrically isolated from the substrate, one of the so-isolated device regions, including any directly underlying semiconductive material of the same conductivity type as that device region, being surrounded within the upper and lower semiconductive layers and the substrate by a tub of opposite conductivity type to that device region, the tub being surrounded within the upper and lower semiconductive layers and the substrate by semiconductive material of opposite conductivity type to the tub.

A method of fabricating an integrated semiconductor structure from a semiconductive substrate which comprises a major region of a first conductivity type, the method comprising the steps of:

• introducing first semiconductor dopant of a second conductivity type opposite to the first conductivity type into the major region to create a vertical isolation region of the second conductivity type;
• introducing second semiconductor dopant of the second conductivity type into the major region to define a first lateral isolation region of the second conductivity type continuous with the vertical isolation region, the second dopant having a greater diffusivity than the first dopant;
• introducing dopant of the first conductivity type into the major region to define a more heavily doped region of the first conductivity type laterally encircled by the first lateral isolation region;
• and
• forming (a) a semiconductive layer over the major region and (b) a transistor from the semiconductive layer such that part of each of the dopants diffuses into the semiconductor layer, the second dopant of the second conductivity type diffusing further into the semiconductive layer than the second dopant of the first conductivity type whereby the first lateral isolation region expands into the semiconductive layer to provide at least partial lateral junction isolation for the transistor while the vertical isolation region expands into the semiconductive layer to at least partially isolate the transistor from first conductivity type material of the major region, the dopant of the first conductivity type diffusing further into the semiconductive layer than the first dopant of the second conductivity type, a buffer region of the first conductivity type thereby being created by expansion of the more heavily doped region into the semiconductive layer so that the buffer region overlies the vertical isolation region and is encircled by the first lateral isolation region.

A method of fabricating an integrated semiconductor structure from a semiconductive substrate which comprises a major region of a first conductivity type, the method comprising the steps of:

• introducing first semiconductor dopant of a second conductivity type opposite to the first conductivity type into the major region to create a vertical isolation region of the second conductivity type;
• introducing second semiconductor dopant of the second conductivity type into the major region to define a first lateral isolation region of the second conductivity type continuous with the vertical isolation region, the second dopant having a greater diffusivity than the first dopant;
• and
• forming (a) a semiconductive layer over the major region and (b) a bipolar transistor from the semiconductive layer such that part of each of the first and second dopants diffuses into the semiconductor layer, the second dopant diffusing further into the semiconductive layer than the first dopant whereby the first lateral isolation region expands into the semiconductive layer to provide at least partial lateral junction isolation for the transistor while the vertical isolation region expands into the semiconductive layer to at least partially isolate the transistor from first conductivity type material of the major region, the transistor having an emitter zone of the first conductivity type, a base zone of the second conductivity type, and continuous first and second collector zones of the first conductivity type, the first collector zone overlying the vertical isolation region, the forming step comprising:
• forming a lower semiconductive layer that includes the first collector zone and a second lateral isolation region of the second conductivity type meeting the first lateral isolation region and surrounding the first collector zone;
• and
• forming, over the lower semiconductive layer, an upper semiconductive layer that includes the second collector zone, the base zone, the emitter zone, and a third lateral isolation region of the second conductivity type meeting the second lateral isolation region and laterally surrounding the second collector zone.