Implied interleaving, a family of systematic interleavers and deinterleavers

An encoder comprising:

• a memory;
• and
• processing means coupled to the memory including
• a) means for writing incoming symbols into the memory,
• b) means for outputting symbols out of the memory at rate higher than the rate of writing into the memory, and applying the read symbols to a channel,
• c) means for implementing D encoders (D being an integer) in the processing means cooperating with the memory, by employing the read symbols in calculations aimed at developing redundant symbols, where each set of D consecutive symbols are distributed to different ones of the implemented D encoders, and
• d) means for applying the redundant symbols to the channel, where the calculations for the D encoders are reset in accordance with a selected implied convolutional interleaving schema.

An encoder comprising:

• a memory;
• and processing means coupled to the memory for
• a) writing incoming symbols into the memory,
• b) outputting symbols out of the memory at a rate higher than the rate of writing into the memory, and applying the read symbols to a channel,
• c) implementing D encoders (D being an integer) by employing the read symbols in calculations aimed at developing redundant symbols, where each set of D consecutive symbols are distributed to different ones of the implemented D encoders and each Dth symbol is employed in the calculations of a particular encoder, and
• d) applying redundant symbols to the channel, where the calculations for the D encoders are reset in accordance with a selected implied interleaving approach from a set that includes regular convolutional implied interleaving and block implied interleaving.

An implied interleaving encoder responsive to a stream of incoming data symbols that is assumed to comprise codewords having N symbols which include redundant symbols and which are interleaved in a convolutional interleaving pattern to an interleaving depth D, for developing the redundant symbols for each of the codewords and inserting them in the stream of incoming data symbols in accordance with the interleaving pattern, including

• a first memory for buffering symbols of the incoming data;
• a plurality of D encoders, each of which develops a set of at least one redundant symbol corresponding to a sequence of symbols that define a data portion of a codeword;
• a first router responsive to output data of the first memory for delivering successive symbols to different ones of the D encoders in a cyclic manner;
• and
• a combiner, responsive to the redundant symbols developed by the D encoders and to output data of the first memory, for applying information arriving at the combiner to a channel, where
• each of the D encoders is arranged to handle codewords that are offset from the codewords handled by the other encoders by at least two symbols.

An implied interleaving encoder responsive to a stream of incoming data symbols that is assumed to comprise codewords having N symbols which include redundant symbols and which are interleaved in a product interleaving pattern to an interleaving depth D, for developing the redundant symbols for each of the codewords and inserting them in the stream of incoming data symbols in accordance with the interleaving pattern, including

• a first memory for buffering symbols of the incoming data;
• a plurality of D encoders, each of which develops a set of at least one redundant symbol corresponding to a sequence of symbols that define a data portion of a codeword;
• an additional encoder responsive to all output data of the first memory for developing at least one additional redundant symbol for each set of preselected number of symbols delivered by the first memory;
• a first router, responsive to output data of the first memory for delivering successive symbols to different ones of the D encoders in cyclic manner;
• a combiner, responsive to the redundant symbols developed by the D encoders, to the redundant symbols developed by the additional encoder, and to output data of the first memory, for applying information arriving at the combiner to a channel.

A systematic convolutional system comprising:

• a plurality of encoders, where each of the encoders outputs the signals applied to the encoder, in the order the signals are applied to the encoder, as well as redundant signals that are developed from a preselected number of the input signals applied to the encoder following a reset signal applied to the encoder;
• means for dispersing applied input signals to said plurality of encoders, where the applied input signals arrive at a predetermined rate;
• means for combining the output signals of the plurality of encoders;
• and
• means for applying a reset signal to at least one of the encoders that is staggered from the other reset signals by more than one period of the rate of arrival of the applied input signals.

A method for encoding and interleaving an applied sequence of input signals arriving at regular intervals, the sequence having a given order, to develop an interleaved output signal comprising the input signals in a sequence having the same given order, the method comprising the steps of:

• routing the input signals to a plurality of encoders;
• in response to the input signals routed to the encoders, the encoders developing a selected number of redundant signals and outputting the redundant signals, where the inserting of redundant signals by any one of the encoders is staggered in time relative to any other one of the encoders by more than one of said intervals;
• and
• routing the output signals of the encoders to an output port.

An encoder comprising:

• a memory;
• and
• processing means coupled to the memory including
• a) means for writing incoming symbols into the memory,
• b) means for outputting symbols out of the memory at rate higher than the rate of writing into the memory, and applying the read symbols to a channel,
• c) means for implementing D encoders (D being an integer) in the processing means cooperating with the memory, by employing the read symbols in calculations aimed at developing redundant symbols, where each set of D consecutive symbols are distributed to different ones of the implemented D encoders, and
• d) means for applying the redundant symbols to the channel, where the calculations for the D encoders are reset in accordance with a selected implied random interleaving schema.

An implied interleaving encoder for creating a data stream output having segments of data and segments of error correction information, comprising:

• a buffer memory adapted to receive and delay a data input communicated at a first bit rate, the buffer memory outputting the data in segments at a second bit rate which is faster than the first bit rate;
• an implied interleaving circuit electrically coupled to the buffer memory, the implied interleaving circuit being adapted to generate the segments of error correction information based on the segments of the data;
• and
• a multiplexing circuit electrically coupled to the buffer memory and the implied interleaving circuit, the multiplexing circuit being adapted to create the data stream by alternatively trasmitting the segments of data from the buffer memory and the segments of error correction information from the implied interleaving circuit into a single data communications channel, wherein the sequence of the data is unchanged.

An implied interleaving encoder for creating a data stream output having segments of data and segments of error correction information, comprising:

• a means for receiving and delaying a data input communicated at a first bit rate;
• a means for transmitting the data in segments at a second bit rate, the second bit rate being greater than the first bit rate;
• a means for generating segments of error correction information based on the segments of the data using a predetermined implied interleaving scheme;
• and
• a means for alternatively transmitting the segments of data and the segments of error correction information into a data communications channel, wherein the sequence of the data is unchanged.

An method for creating a data stream output having segments of data and segments of error correction information using implied interleaving, comprising the steps of:

• receiving and delaying a data input communicated at a first bit rate;
• transmitting the data in segments at a second bit rate, the second bit rate being greater than the first bit rate;
• generating segments of error correction information based on the segments of the data using a predetermined implied interleaving scheme;
• and
• alternatively transmitting the segments of data and the segments of error correction information into a data communications channel, wherein the sequence of the data is unchanged.