Back to results
US 5,898,321 AGranted
Method and apparatus for slew rate and impedance compensating buffer circuits
AssigneeIntel Corporation
InventorsAlper Ilkbahar, Bendik Kleveland
Life of this patent
Estimating the term…
Loading patent…
Loading patent…
AssigneeIntel Corporation
InventorsAlper Ilkbahar, Bendik Kleveland
Estimating the term…
A method and an apparatus for adjusting the slew rate and impedance of a buffer in an integrated circuitry. In one embodiment, an integrated circuit buffer includes a pre-driver circuit, which includes a slew rate compensation circuit, coupled to a driver circuit, which includes an impedance compensation circuit. The slew rate compensation circuit includes parallel connected p-channel transistors to power and parallel connected n-channel transistors to ground to provide a variable resistance to virtual rails for inverter circuits that are included in the pre-driver circuit. The slew rate compensation circuit is digitally controlled with slew rate control signals. The impedance compensation circuit includes parallel connected p-channel transistors to power and parallel connected n-channel transistors to ground from an output node of the buffer. The parallel connected transistors of the impedance compensation circuit are digitally controlled with impedance control signals. The resistance to power and ground from the respective rails of the pre-driver circuit are controlled with the slew rate control signals to adjust the slew rate of data signals being driven by the buffer. The rails are shared among the inverters of the driver circuit to reduce the number of devices used by the buffer, thereby reducing the amount of circuit area and power used by the buffer.
A compensated buffer circuit, comprising:
A method for buffering a data signal generated at an input/output node of an integrated circuit, the method comprising the steps of:
An input/output buffer circuit, comprising:
Dependencies are inferred from the claim text.