Image sensor pixel circuit

An image sensor having a plurality of imager cells arranged in rows and columns, each of said imager cells comprising:

• a photosensitive element providing a photocharge responsive to incoming light;
• a first transistor having a control terminal coupled to a row select line carrying a row select signal to imager cells of a common row to selectively activate imager cells for image data readout, said first transistor operable to transfer said photocharge towards a reference circuit node within said imager cell responsive to said row select signal;
• a second transistor operably coupled to said first transistor, said second transistor operative to selectively set a voltage level at said reference node responsive to a reset signal applied to a control terminal thereof, said reset signal being applied to imager cells of a common row;
• and
• a third transistor having a control terminal coupled to said reference node, and an output terminal coupled to a column data line, said third transistor providing, on said column data line during an image data readout interval for the imager cells of said common row, a first output signal indicative of a reset level at said reference node in a first sampling interval of the readout interval, and a second output signal related to said reference node voltage and indicative of an amount of light incident upon said photosensitive element during a second sampling interval within said readout interval, wherein a comparison is performed between said first and second output signals to extract image data with noise removed.

An image sensor having an array of imager cells arranged in rows and columns, with CMOS timing and logic circuitry applying control signals to said array, each of said imager cells comprising:

• a photosensitive element providing a photocharge responsive to incoming light;
• a first field effect transistor (FET) having a gate terminal coupled to a row select line carrying a row select signal to imager cells of a common row to selectively activate imager cells for image data readout, and a conducting terminal coupled to a reference circuit node, said first FET operable to transfer said photocharge towards said reference circuit node within said imager cell responsive to said row select signal;
• a second FET operably coupled to said first FET, said second FET operative to selectively set a voltage level at said reference node responsive to a reset signal applied to a gate terminal thereof, said reset signal being applied to imager cells of a common row, said second FET having a first conducting terminal coupled to said reference circuit node and a second conducting terminal coupled to a control line common to said common row and carrying a signal VR;
• and
• a third FET having a gate coupled to said reference node, and an output terminal coupled to a column data line, said third transistor providing, on said column date line, during an image data readout interval for the imager cells of said common row, a first output signal indicative of a reset level at said reference node in a first sampling interval of the readout interval, and a second output signal related to said reference node voltage and indicative of an amount of light incident upon said photosensitive element during a second sampling interval within said readout interval, wherein a comparison is performed between said first and second output signals to extract image data with noise removed.