Data processing apparatus and methods including a phase lock loop
AssigneeHewlett-Packard Company
InventorChristopher Huw Williams
Life of this patent
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Abstract
A phase lock loop for recovering a bit clock from a signal containing variations in the bit rate includes mans for resetting the frequency of said phase lock loop to a preset value if the loop loses its lock or if adverse conditions are detected. The loop may be reset if the frequency passes a preset limit or if other apparatus responsive to signal quality or signal to noise ratio detects adverse conditions. In one embodiment the signal is also subjected to automatic gain control and to adaptive filtering, and the frequency may be reset if the A.G.C. and/or the adaptive filter coefficients pass preset thresholds.
Claims10
Apparatus for processing a signal including bits, comprising a phase lock loop for operating at a frequency and recovering a bit clock from the signal, the bits having a tendency to have variations in bit rate, the phase lock loop including a first monitor for the frequency of said phase lock loop, a sampled time filter for processing said signal and for applying thereto an adaptive set of coefficients, a second monitor for monitoring at least one of said coefficients, and a resetter for resetting said loop frequency to a preset value in response to the first monitor indicating the loop frequency is outside a preset range or the second monitor indicating that one or more of said coefficients passes a preset threshold.
Apparatus for processing a signal including bits, comprising a phase lock loop for operating at a frequency and recovering a bit clock from the signal, the bits having a tendency to have variations in bit rate, a monitor for the frequency of said phase lock loop, a detector for an abnormal condition of the signal processing apparatus, other than the phase lock loop frequency being incorrect, the abnormal condition having a tendency to affect the loop frequency, and a resetter responsive to the monitor and detector for resetting said frequency to a preset value in response to the loop frequency being outside a preset range or in response to the detector detecting the abnormal condition.
A method of processing a signal having variations in bit rate to recover a bit clock from the signal, the method comprising supplying said signal to a phase lock loop to obtain a bit clock, monitoring frequency of said phase lock loop, detecting an abnormal condition of apparatus that processes the signal, the abnormal condition being other than the phase lock loop frequency being incorrect, the abnormal condition having a tendency to affect the loop frequency, and resetting the frequency of said phase lock loop to a preset value in response to the loop frequency being monitored as being outside a preset range or if the abnormal condition is detected.
Dependencies are inferred from the claim text.