Field programmable gate array with distributed RAM and increased cell utilization

A field programmable gate array (FPGA), comprising:

• a matrix of rows and columns of programmable logic cells;
• a bus network including a set of bus lines distributed along the rows and columns of logic cells and a set of repeater switch units spaced along said bus lines and selectively connecting associated bus lines to each other, the set of bus lines including local bus lines connectable to logic cells and express bus lines not directly connectable to logic cells but connectable by means of said repeater switch units to associated local bus lines, wherein said matrix of logic cells is organized as blocks of cells with said repeater switch units located between said blocks aligned in rows and columns and arranged around perimeters of said blocks of cells, the repeater switch units thereby allowing express bus lines connected thereto to span more than one block of logic cells;
• and
• a plurality of user-accessible, multibit-addressable memory structures located at corners of each of said blocks of logic cells where said rows and columns of repeater switch units intersect, said memory structures coupled to said bus network, each multibit-addressable memory structure constructed to provide a memory function whereby said memory structures may be addressed, and data stored in and read from said structures, via said bus network, wherein adjacent columns of said memory structures are addressable by bus lines associated with the same columns of blocks of logic cells.

A field programmable gate array (FPGA), comprising:

• a set of input and output terminals,
• a set of bus lines, at least some of which are coupled to said terminals, said set of bus lines including a set of local bus lines, a set of express bus lines, and a set of repeater switch units connecting local bus lines to said express bus lines,
• a plurality of programmable logic cells, each cell having connections to said set of local bus lines, said logic cells being organized into a plurality of blocks of cells, each block having a plurality of said logic cells, wherein each block of cells is connectable to an associated set of local bus lines for that block but not to local bus lines associated with other blocks of cells, said express bus lines spanning multiple blocks of cells, and
• a plurality of user-accessible multibit memory structures, each multibit memory structure associated with a block of cells and having a plurality of address and data ports connectable to bus lines associated with that block of cells.

A field programmable gate array (FPGA), comprising:

• a set of input and output terminals,
• a set of bus lines, at least some of said bus lines being coupled to said terminals, said set of bus lines including a set of local bus lines, a set of express bus lines, and a set of repeater switch units connecting local bus lines to said express bus lines, and
• a plurality of programmable logic cells, each cell having connections to said set of local bus lines,
• wherein each express bus line is connected to non-consecutive repeater switch units.