Common-mode output sensing circuit

An integrated analog to digital converter (ADC), comprising:

• a first comparator having first and second inputs coupled for comparing an analog input signal to a reference voltage to produce a first digital data bit;
• a first ADC stage having a first input coupled for sampling the analog input signal during a first time period and producing a first residue signal at an output during a second time period, the first ADC stage including,
• (1) a first amplifier having a first input coupled for receiving the analog input signal and a first output for providing the first residue signal;
• (2) a first switched capacitor circuit having a first control input responsive to a first clock signal for coupling the first switched capacitor circuit to a first reference conductor during the first time period, and a second control input responsive to a second clock signal for coupling the first switched capacitor circuit to the first output of the first amplifier during the second time period;
• and
• (3) a second switched capacitor circuit having a first control input responsive to the second clock signal for coupling the second switched capacitor circuit to the first reference conductor during the second time period, and a second control input responsive to the first clock signal for coupling the second switched capacitor circuit to the first output of the first amplifier during the first time period.

A wireless communication device, comprising:

• a receiver circuit having an input coupled for receiving a radio frequency carrier signal and an output for providing an analog carrier signal;
• an analog-to-digital converter (ADC), including,
• (1) a first differential amplifier having a differential input for sampling the analog carrier signal during a first clock phase;
• (2) a first switched capacitor circuit having first and second control inputs for respectively coupling the first switched capacitor circuit across first and second common-mode reference conductors during a second clock phase, and across a differential output of the first differential amplifier during the first clock phase;
• (3) a second switched capacitor circuit having first and second control inputs for respectively coupling the second switched capacitor circuit across the first and second common-mode reference conductors during the first clock phase, and across the differential output of the first differential amplifier during the first clock phase;
• (4) a first comparator having an input for receiving the analog carrier signal and providing a first data word during the second clock phase to an output of the ADC;
• (5) a second differential amplifier having a differential input for sampling the analog carrier signal during the second clock phase;
• (6) a third switched capacitor circuit having first and second control inputs for respectively coupling the third switched capacitor circuit across the first and second common-mode reference conductors during the first clock phase, and across a differential output of the second differential amplifier during the second clock phase;
• (7) a fourth switched capacitor circuit having first and second control inputs for respectively coupling the fourth switched capacitor circuit across the first and second common-mode reference conductors during the second clock phase, and across the differential output of the second differential amplifier during the first clock phase;
• (8) a second comparator having an input for receiving the analog carrier signal and providing a second data word to the output of the ADC during the first clock phase;
• and
• a demodulator having an input coupled to the output of the ADC and an output for providing a demodulated signal.

A method of refreshing a common-mode voltage at a first output of an amplifier circuit, comprising the steps of:

• precharging a first capacitance to a desired common-mode voltage during a first clock phase;
• discharging the first capacitance at the first output during a second clock phase;
• precharging a second capacitance to the desired common-mode voltage during a second clock phase;
• and
• discharging the second capacitance at the first output during the first clock phase.