# US 5,894,148 A · Floating gate FPGA cell with counter-doped select device

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- Number: US 5,894,148 A
- Document ID: US5894148A
- Status: Granted
- Kind: A
- Application number: 08/708,074
- Filed: 1996-08-09
- Granted: 1999-04-13
- Earliest claimed: 1996-08-09
- Assignees: GateField Corporation
- Inventors: Jack Zezhong Peng; Robert U. Broze; Kyung Joon Han; Victor Levchenko
- Web page: https://patentgrep.com/patent/US5894148A

## CPC

- H10D 30/0411: {of FETs having floating gates}
- H10D 30/685: {from the channel}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present invention provides for an improved EPROM transistor cell which forms the programming portion of the programmable interconnect interconnect of an FPGA integrated circuit, and a method of manufacturing the EPROM cell. The EPROM cell has a floating gate disposed over a P region of the substrate. Aligned with one edge of the floating gate and at the surface of the substrate is a lightly doped P- region; on the opposite edge of the floating gate is a heavily doped N+ region. A control gate lies over the P-, P substrate and over the N+ region. N+ regions are formed at the opposite edges of the control gate. One N+ region is contiguous to the P- region and forms the source of the EPROM cell and the other N+ region is connected to the N+ region under the control gate and forms the drain of the EPROM cell. This structure allows for easy process control of the V.sub.T of the access transistor formed by the control gate and the P- surface, and of the space charge region formed by the P substrate and the N+ drain of the EPROM cell.

## Claims

### Claim 1

A programming element of an FPGA cell in a substrate of an integrated circuit, said programming element comprising
a first first conductivity-type dopant region in said substrate extending to a principal surface of said substrate;
a first gate electrode oxide layer on said substrate surface over said first first conductivity-type dopant region;
a first gate electrode on said first gate electrode oxide layer forming a floating gate for said FPGA cell, said first gate electrode having a first edge and a second edge;
a second first conductivity-type dopant region in said substrate and abutting said first first-type dopant region and extending to the principal surface of the substrate, said second first conductivity-type region substantially aligned with said first edge of said first gate electrode, said second first conductivity-type dopant region more lightly net doped than said first first conductivity-type dopant region;
a first second conductivity-type dopant region in said substrate and abutting said first first-type dopant region and extending to the principal surface of the substrate, said first second conductivity-type region substantially aligned with said second edge of said first gate electrode;
a second gate electrode oxide layer over said first gate electrode;
a second gate electrode over said second gate electrode oxide layer and extending over said second first conductivity-type dopant region, said second gate electrode forming a control gate for said first gate electrode and a gate for a switching transistor, said second gate electrode having a first edge over first second conductivity-type dopant region; and
a second second conductivity-type dopant region in said substrate and abutting said first first conductivity-type dopant region and said second first conductivity region and extending to the principal surface of the substrate, said second second conductivity-type dopant region substantially aligned with said second edge of said second gate electrode;
whereby said second second conductivity-type region and said first second conductivity-type dopant region respectively form a source and drain for said programming of said FPGA cell.

### Claim 2 (depends on 1)

The programming element of said FPGA cell of claim 1 wherein said first gate electrode oxide layer is in the range of 200 to 400 .ANG..

### Claim 3 (depends on 1)

The programming element of said FPGA cell of claim 1 wherein said second gate electrode oxide layer is in the range of 500 to 700 .ANG..

### Claim 4 (depends on 1)

The programming element of claim 1 wherein said first first-type dopant region has a substantially uniform net dopant concentration across said principal surface.

### Claim 5 (depends on 4)

The programming element of said FPGA cell of claim 4 wherein a net concentration of first-type dopants in said first first-type dopant region is approximately 2.times.10.sup.17 dopants/cm.sup.3.

### Claim 6 (depends on 5)

The programming element of said FPGA cell of claim 5 wherein said first-type dopants comprise P-type dopants and said second-type dopants comprise N-type dopants.

### Claim 7 (depends on 6)

The programming element of said FPGA cell of claim 6 wherein a net concentration of second-type dopants in said first second-type dopant region is approximately 1.times.10.sup.16 dopants/cm.sup.3.

### Claim 8 (depends on 1)

The programming element of said FPGA cell of claim 1 wherein a threshold voltage for said access transistor is less than or approximately equal to 2V above to a source voltage.

### Claim 9 (depends on 1)

The programming element of said FPGA cell of claim 1 wherein programming V.sub.DS is substantially equal to 4V.