FPGA-based processor
AssigneeLucent Technologies Inc.
InventorJocelyn Cloutier
Life of this patent
Estimating the term…
Abstract
A multiprocessor having an input/output controller, a process controller, and a multidimensional arrays of field programmable gate arrays (FPGAs), each FPGA having its own local memory. The multiprocessor may be programmed to function as a single-instruction, multiple-data (SIMD) parallel processor having a matrix of processing elements (PEs), where each FPGA may be programmed to operate as a submatrix array of PEs. The multiprocessor is especially useful for image processing, pattern recognition, and neural network applications.
Claims35
A multiprocessor comprising:
- (a) a multidimensional array of field programmable gate arrays (FPGAs), each FPGA having local memory;
- (b) a process controller, connected to the array of FPGAs;
- and
- (c) an input/output (I/O) controller, connected to the array of FPGAs and to the process controller, wherein:
- the array of FPGAs is adapted to be programmed as a matrix of processing elements (PEs), wherein each FPGA in the array corresponds to two or more PEs;
- the process controller is adapted to control processing implemented by the PEs;
- and
- the I/O controller is adapted to control data flow into and out of the PEs and the process controller.
The invention of claim I, further comprising:
- (d) a global bus interconnecting and adapted to support data transfer between the array of FPGAs, the process controller, and the I/O controller;
- (e) an I/O control bus interconnecting and adapted to support data transfer between the I/O controller and the process controller;
- (f) a program control bus interconnecting and adapted to support data transfer between the process controller and the array of FPGAs, and
- (g) a host system bus adapted to be interconnected to a computer host to support data transfer between the computer host and the I/O controller.
A multiprocessor comprising:
- (a) a first FPGA;
- and
- (b) one or more other FPGAs, connected to the first FPGA, wherein:
- the first FPGA is adapted to be programmed to function exclusively as a process controller for the one or more other FPGAs;
- and
- the one or more other FPGAs are adapted to be programmed to function exclusively as processing elements.
A multiprocessor comprising:
- (a) a multidimensional array of field programmable gate arrays (FPGAs), each FPGA having local memory;
- (b) a process controller, connected to the array of FPGAs;
- and
- (c) an input/output (I/O) controller, connected to the array of FPGAs and to the process controller, wherein:
- the array of FPGAs is adapted to be programmed as one or more processing elements (PEs);
- the process controller is adapted to control processing implemented by the PEs;
- the I/O controller is adapted to control data flow into and out of the PEs and the process controller;
- and
- the PEs are programmed with an optical character recognition algorithm functioning to receive data from an optical scanner in the form of pixels and to output character recognition data.
A multiprocessor comprising:
- (a) a multidimensional array of field programmable gate arrays (FPGAs), each FPGA having local memory;
- (b) a process controller, connected to the array of FPGAs;
- and
- (c) an input/output (I/O) controller, connected to the array of FPGAs and to the process controller, wherein:
- the multidimensional array is a two-dimensional (2D) array, wherein each FPGA in the array is directly connected in north, east, south, and west directions to its four neighboring FPGAs in a torroidal fashion;
- the array of FPGAs is adapted to be programmed as one or more processing elements (PEs);
- the process controller is adapted to control processing implemented by the PEs;
- and
- the I/O controller is adapted to control data flow into and out of the PEs and the process controller.
Dependencies are inferred from the claim text.