NAND-type dynamic RAM having temporary storage register and sense amplifier coupled to multi-open bit lines
AssigneeKabushiki Kaisha Toshiba
InventorsTakehiro Hasegawa, Yukihito Oowaki, Fujio Masuoka, Ryu Ogiwara, Shinichiro Shiratake, Shigeyoshi Watanabe
Life of this patent
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Abstract
A sense amplifier is connected between memory cell arrays, a re-writing register is arranged adjacent to the sense amplifier, first transfer gates are disposed between the sense amplifier and the memory cell arrays, second transfer gates are provided between bit lines of the memory cell arrays and global bit lines, and a gate control circuit for controlling the transfer gates is provided. When readout data is written into the register, the node of the sense amplifier is electrically separated from the bit lines and global bit lines.
Claims10
A dynamic semiconductor memory device comprising:
- a first memory sub-block which includes a first plurality of memory cell arrays;
- a second memory sub-block which includes a second plurality of memory cell arrays;
- a plurality of first signal lines connected to said first and second memory sub-blocks and connected to a plurality of first gates connected between said first and second memory sub-blocks;
- a third memory sub-block which includes a third plurality of memory cell arrays;
- a fourth memory sub-block which includes a fourth plurality of memory cell arrays;
- a plurality of second signal lines connected to said third and fourth memory sub-blocks and connected to a plurality of second gates connected between said third and fourth memory sub-blocks;
- and
- an input/output register receiving a select signal and connected between said second and third memory sub-blocks for inputting/outputting data into/from one of said first to fourth memory sub-blocks based on said select signal.
A dynamic semiconductor memory device comprising:
- a first memory sub-block which includes a first plurality of memory cell arrays;
- a second memory sub-block which includes a second plurality of memory cell arrays;
- a plurality of first signal lines connected to said first and second memory sub-blocks and connected to a plurality of first gates connected between said first and second memory sub-blocks;
- a third memory sub-block which includes a third plurality of memory cell arrays;
- a fourth memory sub-block which includes a fourth plurality of memory cell arrays;
- a plurality of second signal lines connected to said third and fourth memory sub-blocks and connected to a plurality of second gates connected between said third and fourth memory sub-blocks;
- a first input/output register receiving a select signal and connected between said second and third memory sub-blocks for inputting/output data into/from one of said first and second memory sub-blocks based on said select signal;
- and
- a second input/output register receiving said select signal and connected between said second and third memory sub-blocks for inputting/outputting data into/from one of said third and fourth memory sub-blocks based on said select signal.
Dependencies are inferred from the claim text.